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Date: Wed, 30 Mar 2022 09:12:39 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Johan Jonker <jbx6244@...il.com>, heiko@...ech.de,
zhangqing@...k-chips.com
Cc: robh+dt@...nel.org, krzk+dt@...nel.org, mturquette@...libre.com,
sboyd@...nel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] dt-bindings: clock: convert rockchip,px30-cru.txt to
YAML
On 29/03/2022 21:50, Johan Jonker wrote:
> Convert rockchip,px30-cru.txt to YAML.
>
> Changes against original bindings:
> Use compatible string: "rockchip,px30-pmucru"
>
> Signed-off-by: Johan Jonker <jbx6244@...il.com>
> ---
> .../bindings/clock/rockchip,px30-cru.txt | 70 --------------
> .../bindings/clock/rockchip,px30-cru.yaml | 96 +++++++++++++++++++
> 2 files changed, 96 insertions(+), 70 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
> deleted file mode 100644
> index 55e78cdde..000000000
> --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
> +++ /dev/null
> @@ -1,70 +0,0 @@
> -* Rockchip PX30 Clock and Reset Unit
> -
> -The PX30 clock controller generates and supplies clock to various
> -controllers within the SoC and also implements a reset controller for SoC
> -peripherals.
> -
> -Required Properties:
> -
> -- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
> -- compatible: CRU should be "rockchip,px30-cru"
> -- reg: physical base address of the controller and length of memory mapped
> - region.
> -- clocks: A list of phandle + clock-specifier pairs for the clocks listed
> - in clock-names
> -- clock-names: Should contain the following:
> - - "xin24m" for both PMUCRU and CRU
> - - "gpll" for CRU (sourced from PMUCRU)
> -- #clock-cells: should be 1.
> -- #reset-cells: should be 1.
> -
> -Optional Properties:
> -
> -- rockchip,grf: phandle to the syscon managing the "general register files"
> - If missing, pll rates are not changeable, due to the missing pll lock status.
> -
> -Each clock is assigned an identifier and client nodes can use this identifier
> -to specify the clock which they consume. All available clocks are defined as
> -preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
> -used in device tree sources. Similar macros exist for the reset sources in
> -these files.
> -
> -External clocks:
> -
> -There are several clocks that are generated outside the SoC. It is expected
> -that they are defined using standard clock bindings with following
> -clock-output-names:
> - - "xin24m" - crystal input - required,
> - - "xin32k" - rtc clock - optional,
> - - "i2sx_clkin" - external I2S clock - optional,
> - - "gmac_clkin" - external GMAC clock - optional
> -
> -Example: Clock controller node:
> -
> - pmucru: clock-controller@...bc000 {
> - compatible = "rockchip,px30-pmucru";
> - reg = <0x0 0xff2bc000 0x0 0x1000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - };
> -
> - cru: clock-controller@...b0000 {
> - compatible = "rockchip,px30-cru";
> - reg = <0x0 0xff2b0000 0x0 0x1000>;
> - rockchip,grf = <&grf>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> - };
> -
> -Example: UART controller node that consumes the clock generated by the clock
> - controller:
> -
> - uart0: serial@...30000 {
> - compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
> - reg = <0x0 0xff030000 0x0 0x100>;
> - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
> - clock-names = "baudclk", "apb_pclk";
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - };
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml
> new file mode 100644
> index 000000000..aa095f375
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip PX30 Clock and Reset Unit (CRU)
> +
> +maintainers:
> + - Elaine Zhang <zhangqing@...k-chips.com>
> + - Heiko Stuebner <heiko@...ech.de>
> +
> +description: |
> + The PX30 clock controller generates and supplies clocks to various
> + controllers within the SoC and also implements a reset controller for SoC
> + peripherals.
> + Each clock is assigned an identifier and client nodes can use this identifier
> + to specify the clock which they consume. All available clocks are defined as
> + preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
> + used in device tree sources. Similar macros exist for the reset sources in
> + these files.
> + There are several clocks that are generated outside the SoC. It is expected
> + that they are defined using standard clock bindings with following
> + clock-output-names:
> + - "xin24m" - crystal input - required
> + - "xin32k" - rtc clock - optional
> + - "i2sx_clkin" - external I2S clock - optional
> + - "gmac_clkin" - external GMAC clock - optional
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,px30-cru
> + - rockchip,px30-pmucru
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + clocks:
> + minItems: 1
> + items:
> + - description: Clock for both PMUCRU and CRU
> + - description: Clock for CRU (sourced from PMUCRU)
> +
> + clock-names:
> + minItems: 1
> + items:
> + - const: xin24m
> + - const: gpll
You need allOf:if:then: constraining clocks and clock-names per compatible.
Best regards,
Krzysztof
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