linux-kernel - Re: [PATCH v2 5/5] dt-bindings: phy: uniphier: Clean up clock-names and reset-names using compatible string

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Date:   Wed, 30 Mar 2022 19:24:08 +0900
From:   Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc:     Masami Hiramatsu <mhiramat@...nel.org>,
        linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 5/5] dt-bindings: phy: uniphier: Clean up clock-names
 and reset-names using compatible string

Hi Krzysztof,

On 2022/03/30 18:45, Krzysztof Kozlowski wrote:
> On 30/03/2022 11:16, Kunihiko Hayashi wrote:
>> Hi Krzysztof,
>>
>> On 2022/03/30 17:13, Krzysztof Kozlowski wrote:
>>> On 30/03/2022 07:20, Kunihiko Hayashi wrote:
>>>> Instead of "oneOf:" choices, use "allOf:" and "if:" to define
>>>> clock-names
>>>> and reset-names that can be taken by the compatible string.
>>>>
>>>> The order of clock-names and reset-names doesn't change here.
>>>>
>>>> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
>>>> ---
>>>>    .../phy/socionext,uniphier-ahci-phy.yaml      | 73 ++++++++++++------
>>>>    .../phy/socionext,uniphier-pcie-phy.yaml      | 37 ++++++---
>>>>    .../phy/socionext,uniphier-usb3hs-phy.yaml    | 75 +++++++++++++-----
>>>>    .../phy/socionext,uniphier-usb3ss-phy.yaml    | 77 ++++++++++++++-----
>>>>    4 files changed, 188 insertions(+), 74 deletions(-)
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml
>>>> b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml
>>>> index 14f7579e7daa..61d9306e1852 100644
>>>> ---
>>>> a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml
>>>> +++
>>>> b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml
>>>> @@ -30,33 +30,62 @@ properties:
>>>>        minItems: 1
>>>>        maxItems: 2
>>>>
>>>> -  clock-names:
>>>> -    oneOf:
>>>> -      - items:          # for PXs2
>>>> -          - const: link
>>>> -      - items:          # for Pro4
>>>> -          - const: link
>>>> -          - const: gio
>>>> -      - items:          # for others
>>>> -          - const: link
>>>> -          - const: phy
>>>> +  clock-names: true
>>>>
>>>>      resets:
>>>>        minItems: 2
>>>>        maxItems: 6
>>>>
>>>> -  reset-names:
>>>> -    oneOf:
>>>> -      - items:          # for Pro4
>>>> -          - const: link
>>>> -          - const: gio
>>>> -          - const: phy
>>>> -          - const: pm
>>>> -          - const: tx
>>>> -          - const: rx
>>>> -      - items:          # for others
>>>> -          - const: link
>>>> -          - const: phy
>>>> +  reset-names: true
>>>> +
>>>> +allOf:
>>>> +  - if:
>>>> +      properties:
>>>> +        compatible:
>>>> +          contains:
>>>> +            const: socionext,uniphier-pro4-ahci-phy
>>>> +    then:
>>>> +      properties:
>>>> +        clock-names:
>>>> +          items:
>>>> +            - const: link
>>>> +            - const: gio
>>>> +        reset-names:
>>>> +          items:
>>>> +            - const: link
>>>> +            - const: gio
>>>> +            - const: phy
>>>> +            - const: pm
>>>> +            - const: tx
>>>> +            - const: rx
>>>
>>> Constrain also everywhere clocks and resets, so here should be:
>>>     resets:
>>>       minItems: 6
>>>       maxItems: 6
>>
>> If I put the constraint here, it would conflict with the original one.
>> Should I also replace the original resets
>>
>>       resets:
>>         minItems: 2
>>         maxItems: 6
>>
>> with "resets: true"?
> 
> It should not conflict. Check the bindings for Samsung Exynos clock I
> sent you last time. In the main "properties" you put the widest
> constraints, like you have now (2-6). Then for each compatible you
> narrow it (2-2, 6-6).
> 
> You can later test it by adding/removing clocks to check if constraints
> are properly working.

I understand. The main "properties" should be the widest constraints,
and I checked that Exynos clock is set to the widest (1-10).
I'll add the constraints.

Thank you,

---
Best Regards
Kunihiko Hayashi