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Message-ID: <4dcad1c3-c471-ce70-eecb-17f803f737b4@microchip.com>
Date: Wed, 30 Mar 2022 13:26:17 +0000
From: <Claudiu.Beznea@...rochip.com>
To: <michael@...le.cc>, <Kavyasree.Kotagiri@...rochip.com>,
<Nicolas.Ferre@...rochip.com>
CC: <arnd@...db.de>, <olof@...om.net>, <soc@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski@...onical.com>,
<alexandre.belloni@...tlin.com>
Subject: Re: [PATCH v2 6/7] ARM: dts: lan966x: add flexcom I2C nodes
On 04.03.2022 17:35, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add all I2C nodes of the flexcom IP blocks. The driver supports
> FIFO, DMA or both combined. But the latter isn't working correctly.
> Thus, skip the fifo-size property for now. DMA is doing single byte
> reads in this case.
>
> Keep the nodes disabled by default.
>
> Signed-off-by: Michael Walle <michael@...le.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---
> arch/arm/boot/dts/lan966x.dtsi | 65 ++++++++++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> index a61d394ad04d..95d58bdca3f0 100644
> --- a/arch/arm/boot/dts/lan966x.dtsi
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -120,6 +120,19 @@ spi0: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c0: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(3)>,
> + <&dma0 AT91_XDMAC_DT_PERID(2)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx1: flexcom@...44000 {
> @@ -158,6 +171,19 @@ spi1: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c1: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(5)>,
> + <&dma0 AT91_XDMAC_DT_PERID(4)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> trng: rng@...48000 {
> @@ -213,6 +239,19 @@ spi2: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c2: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
> + <&dma0 AT91_XDMAC_DT_PERID(6)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> flx3: flexcom@...64000 {
> @@ -251,6 +290,19 @@ spi3: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c3: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(9)>,
> + <&dma0 AT91_XDMAC_DT_PERID(8)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> dma0: dma-controller@...68000 {
> @@ -308,6 +360,19 @@ spi4: spi@400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c4: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(11)>,
> + <&dma0 AT91_XDMAC_DT_PERID(10)>;
> + dma-names = "tx", "rx";
> + clocks = <&nic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> };
>
> timer0: timer@...8c000 {
> --
> 2.30.2
>
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