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Date: Fri, 1 Apr 2022 10:31:57 -0400 From: Sasha Levin <sashal@...nel.org> To: linux-kernel@...r.kernel.org, stable@...r.kernel.org Cc: Sung Joon Kim <sungkim@....com>, Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@....com>, Jun Lei <Jun.Lei@....com>, Jasdeep Dhillon <jdhillon@....com>, Daniel Wheeler <daniel.wheeler@....com>, Alex Deucher <alexander.deucher@....com>, Sasha Levin <sashal@...nel.org>, harry.wentland@....com, sunpeng.li@....com, Rodrigo.Siqueira@....com, christian.koenig@....com, Xinhui.Pan@....com, airlied@...ux.ie, daniel@...ll.ch, wenjing.liu@....com, george.shen@....com, Jimmy.Kizito@....com, Wesley.Chalmers@....com, Jerry.Zuo@....com, amd-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org Subject: [PATCH AUTOSEL 5.16 050/109] drm/amd/display: reset lane settings after each PHY repeater LT From: Sung Joon Kim <sungkim@....com> [ Upstream commit 3b853c316c9321e195414a6fb121d1c2d45b1e87 ] [why] In LTTPR non-transparent mode, we need to reset the cached lane settings before performing link training on the next PHY repeater. Otherwise, the cached lane settings will be used for the next clock recovery e.g. VS = MAX (3) which should not be the case according to the DP specs. We expect to use minimum lane settings on each clock recovery sequence. [how] Reset DPCD and HW lane settings on each repeater LT. Set training pattern to 0 for the repeater that failed LT at the proper place. Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@....com> Reviewed-by: Jun Lei <Jun.Lei@....com> Acked-by: Jasdeep Dhillon <jdhillon@....com> Signed-off-by: Sung Joon Kim <sungkim@....com> Tested-by: Daniel Wheeler <daniel.wheeler@....com> Signed-off-by: Alex Deucher <alexander.deucher@....com> Signed-off-by: Sasha Levin <sashal@...nel.org> --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 135ea1c422f2..f46aa7f8c35d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2124,21 +2124,26 @@ static enum link_training_result dp_perform_8b_10b_link_training( repeater_id--) { status = perform_clock_recovery_sequence(link, lt_settings, repeater_id); - if (status != LINK_TRAINING_SUCCESS) + if (status != LINK_TRAINING_SUCCESS) { + repeater_training_done(link, repeater_id); break; + } status = perform_channel_equalization_sequence(link, lt_settings, repeater_id); + repeater_training_done(link, repeater_id); + if (status != LINK_TRAINING_SUCCESS) break; - repeater_training_done(link, repeater_id); + for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { + lt_settings->dpcd_lane_settings[lane].raw = 0; + lt_settings->hw_lane_settings[lane].VOLTAGE_SWING = 0; + lt_settings->hw_lane_settings[lane].PRE_EMPHASIS = 0; + } } - - for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++) - lt_settings->dpcd_lane_settings[lane].raw = 0; } if (status == LINK_TRAINING_SUCCESS) { -- 2.34.1
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