linux-kernel - [irqchip: irq/irqchip-fixes] irqchip/gic-v3: Fix GICR

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Message-ID: <164917319947.389.16591150926204042875.tip-bot2@tip-bot2>
Date:   Tue, 05 Apr 2022 15:39:59 -0000
From:   "irqchip-bot for Marc Zyngier" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Marc Zyngier <maz@...nel.org>, stable@...r.kernel.org,
        Andre Przywara <andre.przywara@....com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        tglx@...utronix.de
Subject: [irqchip: irq/irqchip-fixes] irqchip/gic-v3: Fix GICR_CTLR.RWP polling

The following commit has been merged into the irq/irqchip-fixes branch of irqchip:

Commit-ID:     0df6664531a12cdd8fc873f0cac0dcb40243d3e9
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/0df6664531a12cdd8fc873f0cac0dcb40243d3e9
Author:        Marc Zyngier <maz@...nel.org>
AuthorDate:    Tue, 15 Mar 2022 16:50:32 
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Tue, 05 Apr 2022 16:33:13 +01:00

irqchip/gic-v3: Fix GICR_CTLR.RWP polling

It turns out that our polling of RWP is totally wrong when checking
for it in the redistributors, as we test the *distributor* bit index,
whereas it is a different bit number in the RDs... Oopsie boo.

This is embarassing. Not only because it is wrong, but also because
it took *8 years* to notice the blunder...

Just fix the damn thing.

Fixes: 021f653791ad ("irqchip: gic-v3: Initial support for GICv3")
Signed-off-by: Marc Zyngier <maz@...nel.org>
Cc: stable@...r.kernel.org
Reviewed-by: Andre Przywara <andre.przywara@....com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Link: https://lore.kernel.org/r/20220315165034.794482-2-maz@kernel.org
---
 drivers/irqchip/irq-gic-v3.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 0efe1a9..9b63165 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -206,11 +206,11 @@ static inline void __iomem *gic_dist_base(struct irq_data *d)
 	}
 }
 
-static void gic_do_wait_for_rwp(void __iomem *base)
+static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
 {
 	u32 count = 1000000;	/* 1s! */
 
-	while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
+	while (readl_relaxed(base + GICD_CTLR) & bit) {
 		count--;
 		if (!count) {
 			pr_err_ratelimited("RWP timeout, gone fishing\n");
@@ -224,13 +224,13 @@ static void gic_do_wait_for_rwp(void __iomem *base)
 /* Wait for completion of a distributor change */
 static void gic_dist_wait_for_rwp(void)
 {
-	gic_do_wait_for_rwp(gic_data.dist_base);
+	gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
 }
 
 /* Wait for completion of a redistributor change */
 static void gic_redist_wait_for_rwp(void)
 {
-	gic_do_wait_for_rwp(gic_data_rdist_rd_base());
+	gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
 }
 
 #ifdef CONFIG_ARM64