linux-kernel - [PATCH] x86: Prefer MWAIT over HALT on AMD processors

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Message-ID: <20220405130021.557880-1-wyes.karny@amd.com>
Date:   Tue, 5 Apr 2022 18:30:21 +0530
From:   Wyes Karny <wyes.karny@....com>
To:     <linux-kernel@...r.kernel.org>
CC:     <Lewis.Carroll@....com>, <Mario.Limonciello@....com>,
        <gautham.shenoy@....com>, <Ananth.Narayan@....com>,
        <bharata@....com>, <len.brown@...el.com>, <x86@...nel.org>,
        <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
        <dave.hansen@...ux.intel.com>, <hpa@...or.com>,
        <peterz@...radead.org>, <chang.seok.bae@...el.com>,
        <keescook@...omium.org>, <metze@...ba.org>,
        <zhengqi.arch@...edance.com>, <mark.rutland@....com>
Subject: [PATCH] x86: Prefer MWAIT over HALT on AMD processors

From: Lewis Caroll <lewis.carroll@....com>

Currently in the absence of the cpuidle driver (eg: when global
C-States are disabled in the BIOS or when cpuidle is driver is not
compiled in), the default idle state on AMD Zen processors uses the
HALT instruction even though there is support for MWAIT instruction
which is more efficient than HALT.

The below table represents the exit latency for HALT and MWAIT on AMD
Zen 3 system.
Exit latency is measured by issuing a wakeup (IPI) to other
CPU and measuring how many clock cycles it took to wakeup.
Each iteration measures 10K wakeups by pinning source and
destination.

HALT:

25.0000th percentile  :      1900 ns
50.0000th percentile  :      2000 ns
75.0000th percentile  :      2300 ns
90.0000th percentile  :      2500 ns
95.0000th percentile  :      2600 ns
99.0000th percentile  :      2800 ns
99.5000th percentile  :      3000 ns
99.9000th percentile  :      3400 ns
99.9500th percentile  :      3600 ns
99.9900th percentile  :      5900 ns
  Min latency         :      1700 ns
  Max latency         :      5900 ns
Total Samples      9999

MWAIT:

25.0000th percentile  :      1400 ns
50.0000th percentile  :      1500 ns
75.0000th percentile  :      1700 ns
90.0000th percentile  :      1800 ns
95.0000th percentile  :      1900 ns
99.0000th percentile  :      2300 ns
99.5000th percentile  :      2500 ns
99.9000th percentile  :      3200 ns
99.9500th percentile  :      3500 ns
99.9900th percentile  :      4600 ns
  Min latency         :      1200 ns
  Max latency         :      4600 ns
Total Samples      9997

Improvement: 21.74%

A similar trend is observed on older Zen processors also.

Here we enable MWAIT instruction as the default idle call for AMD
Zen processors which support MWAIT. We retain the existing behaviour
for older processors which depend on HALT.

NOTE: This change only impacts the default idle behaviour in the
absence of cpuidle driver. If the cpuidle driver is present, it
controls the processor idle behaviour.

Fixes: commit b253149b843f ("sched/idle/x86: Restore mwait_idle() to fix boot hangs, to improve power savings and to improve performance")
Signed-off-by: Lewis Caroll <lewis.carroll@....com>
Signed-off-by: Wyes Karny <Wyes.Karny@....com>
---
 arch/x86/kernel/process.c | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 81d8ef036637..952d0382354b 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -809,19 +809,34 @@ static void amd_e400_idle(void)
 	raw_local_irq_enable();
 }
 
+/*
+ * Intel and AMD Zen processors allow MWAIT early on.
+ */
+static inline bool early_mwait_supported(const struct cpuinfo_x86 *c)
+{
+	if (c->x86_vendor == X86_VENDOR_INTEL)
+		return true;
+
+	if (c->x86_vendor == X86_VENDOR_AMD && cpu_has(c, X86_FEATURE_ZEN))
+		return true;
+
+	return false;
+}
+
 /*
  * Intel Core2 and older machines prefer MWAIT over HALT for C1.
  * We can't rely on cpuidle installing MWAIT, because it will not load
  * on systems that support only C1 -- so the boot default must be MWAIT.
  *
- * Some AMD machines are the opposite, they depend on using HALT.
+ * Even AMD Zen processors prefer MWAIT over HALT. But older AMD processors
+ * depend on HALT.
  *
  * So for default C1, which is used during boot until cpuidle loads,
- * use MWAIT-C1 on Intel HW that has it, else use HALT.
+ * use MWAIT-C1 on Intel and AMD HW that have it, else use HALT.
  */
 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 {
-	if (c->x86_vendor != X86_VENDOR_INTEL)
+	if (!early_mwait_supported(c))
 		return 0;
 
 	if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
-- 
2.27.0