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Message-ID: <Yk0gnG+oqpARzC+m@lahna>
Date:   Wed, 6 Apr 2022 08:09:48 +0300
From:   Mika Westerberg <mika.westerberg@...ux.intel.com>
To:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc:     linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
        Andy Shevchenko <andy@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [PATCH v1 1/1] pinctrl: alderlake: Fix register offsets for
 ADL-N variant

On Tue, Apr 05, 2022 at 08:02:51PM +0300, Andy Shevchenko wrote:
> It appears that almost traditionally the N variants have deviations
> in the register offsets in comparison to S one. This is the case
> for Intel Alder Lake as well. Fix register offsets for ADL-N variant.
> 
> Fixes: 114b610b9048 ("pinctrl: alderlake: Add Intel Alder Lake-N pin controller support")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>

Acked-by: Mika Westerberg <mika.westerberg@...ux.intel.com>

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