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Message-ID: <ee039d8a-fe91-d0a8-5b8f-5fc879e6aa8d@microchip.com>
Date: Wed, 6 Apr 2022 09:44:04 +0000
From: <Claudiu.Beznea@...rochip.com>
To: <michael@...le.cc>, <Kavyasree.Kotagiri@...rochip.com>,
<Nicolas.Ferre@...rochip.com>
CC: <arnd@...db.de>, <olof@...om.net>, <soc@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski@...onical.com>,
<alexandre.belloni@...tlin.com>, <Tudor.Ambarus@...rochip.com>
Subject: Re: [PATCH v3 7/7] ARM: dts: lan966x: add basic Kontron KSwitch D10
support
On 05.04.2022 19:08, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add basic support for the Kontron KSwitch D10 MMT. It comes in two
> variants: "6G-2GS" which features 6 Gigabit copper ports and two SFP
> cages and "8G" which features 6 Gigbabit copper ports (where two are
> 2.5G capable).
>
> For now the following is supported and working:
> - Kernel console
> - SFP cages I2C bus and mux
> - SPI
> - SGPIO
> - Watchdog
>
> Signed-off-by: Michael Walle <michael@...le.cc>
Reviewed-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
> ---
> arch/arm/boot/dts/Makefile | 4 +-
> ...lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts | 77 +++++++++++++++++++
> .../lan966x-kontron-kswitch-d10-mmt-8g.dts | 13 ++++
> .../dts/lan966x-kontron-kswitch-d10-mmt.dtsi | 75 ++++++++++++++++++
> 4 files changed, 168 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
> create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
> create mode 100644 arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 7c16f8a2b738..54beef7c1810 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -742,7 +742,9 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \
> imx7ulp-com.dtb \
> imx7ulp-evk.dtb
> dtb-$(CONFIG_SOC_LAN966) += \
> - lan966x-pcb8291.dtb
> + lan966x-pcb8291.dtb \
> + lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
> + lan966x-kontron-kswitch-d10-mmt-8g.dtb
> dtb-$(CONFIG_SOC_LS1021A) += \
> ls1021a-moxa-uc-8410a.dtb \
> ls1021a-qds.dtb \
> diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
> new file mode 100644
> index 000000000000..9cf0b791a355
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-6g-2gs.dts
> @@ -0,0 +1,77 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for the Kontron KSwitch D10 MMT 6G-2GS
> + */
> +
> +/dts-v1/;
> +#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
> +
> +/ {
> + model = "Kontron KSwitch D10 MMT 6G-2GS";
> + compatible = "kontron,kswitch-d10-mmt-6g-2gs", "kontron,s1921",
> + "microchip,lan9668", "microchip,lan966";
> +
> + i2cmux {
> + compatible = "i2c-mux-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + mux-gpios = <&sgpio_out 3 2 GPIO_ACTIVE_HIGH>,
> + <&sgpio_out 3 3 GPIO_ACTIVE_HIGH>;
> + i2c-parent = <&i2c4>;
> +
> + i2c4_0: i2c@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4_1: i2c@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + sfp0: sfp0 {
> + compatible = "sff,sfp";
> + i2c-bus = <&i2c4_0>;
> + los-gpios = <&sgpio_in 1 0 GPIO_ACTIVE_HIGH>;
> + mod-def0-gpios = <&sgpio_in 1 1 GPIO_ACTIVE_LOW>;
> + maximum-power-milliwatt = <2500>;
> + tx-disable-gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>;
> + tx-fault-gpios = <&sgpio_in 0 2 GPIO_ACTIVE_HIGH>;
> + rate-select0-gpios = <&sgpio_out 2 0 GPIO_ACTIVE_HIGH>;
> + rate-select1-gpios = <&sgpio_out 2 1 GPIO_ACTIVE_HIGH>;
> + };
> +
> + sfp1: sfp1 {
> + compatible = "sff,sfp";
> + i2c-bus = <&i2c4_1>;
> + los-gpios = <&sgpio_in 1 2 GPIO_ACTIVE_HIGH>;
> + mod-def0-gpios = <&sgpio_in 1 3 GPIO_ACTIVE_LOW>;
> + maximum-power-milliwatt = <2500>;
> + tx-disable-gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>;
> + tx-fault-gpios = <&sgpio_in 0 3 GPIO_ACTIVE_HIGH>;
> + rate-select0-gpios = <&sgpio_out 2 2 GPIO_ACTIVE_HIGH>;
> + rate-select1-gpios = <&sgpio_out 2 3 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&flx4 {
> + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> + status = "okay";
> +
> + i2c4: i2c@600 {
> + pinctrl-0 = <&fc4_b_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> + };
> +};
> +
> +&gpio {
> + fc4_b_pins: fc4-b-i2c-pins {
> + /* SCL, SDA */
> + pins = "GPIO_57", "GPIO_58";
> + function = "fc4_b";
> + };
> +};
> diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
> new file mode 100644
> index 000000000000..4b35f6c46e7f
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt-8g.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree file for the Kontron KSwitch D10 MMT 8G
> + */
> +
> +/dts-v1/;
> +#include "lan966x-kontron-kswitch-d10-mmt.dtsi"
> +
> +/ {
> + model = "Kontron KSwitch D10 MMT 8G";
> + compatible = "kontron,kswitch-d10-mmt-8g", "kontron,s1921",
> + "microchip,lan9668", "microchip,lan966";
> +};
> diff --git a/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
> new file mode 100644
> index 000000000000..4178fb0bd9c5
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x-kontron-kswitch-d10-mmt.dtsi
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Common part of the device tree for the Kontron KSwitch D10 MMT
> + */
> +
> +/dts-v1/;
> +#include "lan966x.dtsi"
> +
> +/ {
> + aliases {
> + serial0 = &usart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + gpio-restart {
> + compatible = "gpio-restart";
> + gpios = <&gpio 56 GPIO_ACTIVE_LOW>;
> + priority = <200>;
> + };
> +};
> +
> +&flx0 {
> + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
> + status = "okay";
> +
> + usart0: serial@200 {
> + pinctrl-0 = <&usart0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> + };
> +};
> +
> +&gpio {
> + usart0_pins: usart0-pins {
> + /* RXD, TXD */
> + pins = "GPIO_25", "GPIO_26";
> + function = "fc0_b";
> + };
> +
> + sgpio_a_pins: sgpio-a-pins {
> + /* SCK, D0, D1 */
> + pins = "GPIO_32", "GPIO_33", "GPIO_34";
> + function = "sgpio_a";
> + };
> +
> + sgpio_b_pins: sgpio-b-pins {
> + /* LD */
> + pins = "GPIO_64";
> + function = "sgpio_b";
> + };
> +};
> +
> +&sgpio {
> + pinctrl-0 = <&sgpio_a_pins>, <&sgpio_b_pins>;
> + pinctrl-names = "default";
> + bus-frequency = <8000000>;
> + /* arbitrary range because all GPIOs are in software mode */
> + microchip,sgpio-port-ranges = <0 11>;
> + status = "okay";
> +
> + sgpio_in: gpio@0 {
> + ngpios = <128>;
> + };
> +
> + sgpio_out: gpio@1 {
> + ngpios = <128>;
> + };
> +};
> +
> +&watchdog {
> + status = "okay";
> +};
> --
> 2.30.2
>
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