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Date: Wed, 6 Apr 2022 12:04:08 +0200 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com> To: broonie@...nel.org Cc: matthias.bgg@...il.com, linux-spi@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org, nfraprado@...labora.com, kernel@...labora.com, AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com> Subject: [PATCH 6/7] spi: mt65xx: Add kerneldoc for driver structures One of the two structures was already partially documented, but not in kerneldoc format: enhance readability by adding the missing documentation bits and use kerneldoc. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com> --- drivers/spi/spi-mt65xx.c | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index c5b8aecfada6..8bd0b7335ea0 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -95,21 +95,43 @@ #define DMA_ADDR_EXT_BITS (36) #define DMA_ADDR_DEF_BITS (32) +/** + * struct mtk_spi_compatible - device data structure + * @need_pad_sel: Enable pad (pins) selection in SPI controller + * @must_tx: Must explicitly send dummy TX bytes to do RX only transfer + * @enhance_timing: Enable adjusting cfg register to enhance time accuracy + * @dma_ext: DMA address extension supported + * @no_need_unprepare: Don't unprepare the SPI clk during runtime + * @ipm_design: Adjust/extend registers to support IPM design IP features + */ struct mtk_spi_compatible { bool need_pad_sel; - /* Must explicitly send dummy Tx bytes to do Rx only transfer */ bool must_tx; - /* some IC design adjust cfg register to enhance time accuracy */ bool enhance_timing; - /* some IC support DMA addr extension */ bool dma_ext; - /* some IC no need unprepare SPI clk */ bool no_need_unprepare; - /* IPM design adjust and extend register to support more features */ bool ipm_design; - }; +/** + * struct mtk_spi - SPI driver instance + * @base: Start address of the SPI controller registers + * @state: SPI controller state + * @pad_num: Number of pad_sel entries + * @pad_sel: Groups of pins to select + * @parent_clk: Parent of sel_clk + * @sel_clk: SPI master SCK clock + * @spi_clk: Peripheral clock + * @cur_transfer: Currently processed SPI transfer + * @xfer_len: Number of bytes to transfer + * @num_xfered: Number of transferred bytes + * @tx_sgl: TX transfer scatterlist + * @rx_sgl: RX transfer scatterlist + * @tx_sgl_len: Size of TX DMA transfer + * @rx_sgl_len: Size of RX DMA transfer + * @dev_comp: Device data structure + * @spi_clk_hz: Current SPI clock in Hz + */ struct mtk_spi { void __iomem *base; u32 state; -- 2.35.1
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