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Message-ID: <bc71266a-50c9-ef0f-6bc1-20df79782d32@linaro.org>
Date: Thu, 7 Apr 2022 14:05:20 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>,
broonie@...nel.org, robh+dt@...nel.org, krzk+dt@...nel.org
Cc: nicolas.ferre@...rochip.com, alexandre.belloni@...tlin.com,
claudiu.beznea@...rochip.com, tudor.ambarus@...rochip.com,
linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
UNGLinuxDriver@...rochip.com, Manohar.Puri@...rochip.com
Subject: Re: [PATCH] spi: atmel,quadspi: Define lan966x QSPI
On 07/04/2022 12:54, Kavyasree Kotagiri wrote:
> LAN966x SoC supports 3 QSPI controllers. Each of them support
> data and clock frequency upto 100Mhz DDR and QUAD protocol.
>
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>
> ---
> Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> index 1d493add4053..100d6e7f2748 100644
> --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> @@ -19,6 +19,7 @@ properties:
> - microchip,sam9x60-qspi
> - microchip,sama7g5-qspi
> - microchip,sama7g5-ospi
> + - microchip,lan966x-qspi
Expect the comment you got about wildcard, please also put it in
alphabetical order. As you can check, the other entries are ordered.
Best regards,
Krzysztof
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