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Message-ID: <1369ae65-5455-f217-c770-570e2472ba47@linaro.org>
Date: Thu, 7 Apr 2022 14:13:11 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>,
arnd@...db.de, robh+dt@...nel.org, krzk+dt@...nel.org,
alexandre.belloni@...tlin.com, olof@...om.net, soc@...nel.org,
nicolas.ferre@...rochip.com
Cc: linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, UNGLinuxDriver@...rochip.com,
tudor.ambarus@...rochip.com, Manohar.Puri@...rochip.com
Subject: Re: [PATCH 2/2] ARM: dts: lan966x-pcb8291: Add QSPI0 and SPI NOR
memory nodes
On 07/04/2022 12:58, Kavyasree Kotagiri wrote:
> Enable QSPI0 controller and sst26vf016b SPI-NOR flash present on it.
>
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>
> ---
> arch/arm/boot/dts/lan966x-pcb8291.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
> index 3281af90ac6d..99d96d46661d 100644
> --- a/arch/arm/boot/dts/lan966x-pcb8291.dts
> +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
> @@ -62,3 +62,18 @@
> &watchdog {
> status = "okay";
> };
> +
> +&qspi0 {
> + status = "okay";
> +
> + spi-flash@0 {
Just "flash" please (to be generic).
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
Why do you need address/size cells here? You don't have any children.
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + m25p,fast-read;
> + };
> +};
Best regards,
Krzysztof
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