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Message-ID: <YlBqrAApeb8rV9WJ@zn.tnic>
Date: Fri, 8 Apr 2022 19:02:36 +0200
From: Borislav Petkov <bp@...en8.de>
To: Medad CChien <medadyoung@...il.com>
Cc: rric@...nel.org, james.morse@....com, tony.luck@...el.com,
mchehab@...nel.org, robh+dt@...nel.org, benjaminfair@...gle.com,
yuenn@...gle.com, venture@...gle.com, KWLIU@...oton.com,
YSCHU@...oton.com, JJLIU0@...oton.com, KFTING@...oton.com,
avifishman70@...il.com, tmaimon77@...il.com, tali.perry1@...il.com,
ctcchien@...oton.com, linux-edac@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
openbmc@...ts.ozlabs.org
Subject: Re: [PATCH v6 1/3] ARM: dts: nuvoton: Add memory controller node
On Tue, Mar 22, 2022 at 11:01:50AM +0800, Medad CChien wrote:
> ECC must be configured in the BootBlock header.
> Then, you can read error counts via
> the EDAC kernel framework.
>
> Signed-off-by: Medad CChien <ctcchien@...oton.com>
> ---
> arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> index 3696980a3da1..ba542b26941e 100644
> --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi
> @@ -106,6 +106,13 @@
> interrupt-parent = <&gic>;
> ranges;
>
> + mc: memory-controller@...24000 {
> + compatible = "nuvoton,npcm750-memory-controller";
> + reg = <0x0 0xf0824000 0x0 0x1000>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> rstc: rstc@...01000 {
> compatible = "nuvoton,npcm750-reset";
> reg = <0xf0801000 0x70>;
> --
This needs an ACK from devicetree folks.
--
Regards/Gruss,
Boris.
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