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Message-ID: <CADnq5_NY-2sX+5Q7LZWpRqPz0dQg4-xgqSx2_-qzvZ8Ar=J_YA@mail.gmail.com>
Date: Fri, 8 Apr 2022 15:08:33 -0400
From: Alex Deucher <alexdeucher@...il.com>
To: Richard Gong <richard.gong@....com>
Cc: "Deucher, Alexander" <alexander.deucher@....com>,
Christian Koenig <christian.koenig@....com>,
xinhui pan <xinhui.pan@....com>,
Dave Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
"Limonciello, Mario" <mario.limonciello@....com>,
Maling list - DRI developers
<dri-devel@...ts.freedesktop.org>,
amd-gfx list <amd-gfx@...ts.freedesktop.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCHv2] drm/amdgpu: disable ASPM on Intel AlderLake based systems
On Fri, Apr 8, 2022 at 3:05 PM Richard Gong <richard.gong@....com> wrote:
>
> Active State Power Management (ASPM) feature is enabled since kernel 5.14.
> There are some AMD GFX cards (such as WX3200 and RX640) that cannot be
> used with Intel AlderLake based systems to enable ASPM. Using these GFX
> cards as video/display output, Intel Alder Lake based systems will hang
> during suspend/resume.
>
> Add extra check to disable ASPM on Intel AlderLake based systems.
>
> Fixes: 0064b0ce85bb ("drm/amd/pm: enable ASPM by default")
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1885
> Signed-off-by: Richard Gong <richard.gong@....com>
Reviewed-by: Alex Deucher <alexander.deucher@....com>
> ---
> v2: correct commit description
> move the check from chip family to problematic platform
> ---
> drivers/gpu/drm/amd/amdgpu/vi.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 039b90cdc3bc..8b4eaf54b23e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -81,6 +81,10 @@
> #include "mxgpu_vi.h"
> #include "amdgpu_dm.h"
>
> +#if IS_ENABLED(CONFIG_X86_64)
> +#include <asm/intel-family.h>
> +#endif
> +
> #define ixPCIE_LC_L1_PM_SUBSTATE 0x100100C6
> #define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
> #define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
> @@ -1134,13 +1138,24 @@ static void vi_enable_aspm(struct amdgpu_device *adev)
> WREG32_PCIE(ixPCIE_LC_CNTL, data);
> }
>
> +static bool intel_core_apsm_chk(void)
> +{
> +#if IS_ENABLED(CONFIG_X86_64)
> + struct cpuinfo_x86 *c = &cpu_data(0);
> +
> + return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
> +#else
> + return false;
> +#endif
> +}
> +
> static void vi_program_aspm(struct amdgpu_device *adev)
> {
> u32 data, data1, orig;
> bool bL1SS = false;
> bool bClkReqSupport = true;
>
> - if (!amdgpu_device_should_use_aspm(adev))
> + if (!amdgpu_device_should_use_aspm(adev) || intel_core_apsm_chk())
> return;
>
> if (adev->flags & AMD_IS_APU ||
> --
> 2.25.1
>
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