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Message-ID: <20220408052150.22536-2-johnson.wang@mediatek.com>
Date: Fri, 8 Apr 2022 13:21:49 +0800
From: Johnson Wang <johnson.wang@...iatek.com>
To: <cw00.choi@...sung.com>, <krzk+dt@...nel.org>,
<robh+dt@...nel.org>, <kyungmin.park@...sung.com>
CC: <khilman@...nel.org>, <linux-pm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>, <jia-wei.chang@...iatek.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Johnson Wang <johnson.wang@...iatek.com>
Subject: [PATCH v2 1/2] dt-bindings: devfreq: mediatek: Add mtk cci devfreq dt-bindings
Add devicetree binding of mtk cci devfreq on MediaTek SoC.
Signed-off-by: Johnson Wang <johnson.wang@...iatek.com>
Signed-off-by: Jia-Wei Chang <jia-wei.chang@...iatek.com>
---
.../devicetree/bindings/devfreq/mtk-cci.yaml | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/mtk-cci.yaml
diff --git a/Documentation/devicetree/bindings/devfreq/mtk-cci.yaml b/Documentation/devicetree/bindings/devfreq/mtk-cci.yaml
new file mode 100644
index 000000000000..ef4ea951025c
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/mtk-cci.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/mtk-cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
+
+maintainers:
+ - Jia-Wei Chang <jia-wei.chang@...iatek.com>
+
+description: |
+ MediaTek Cache Coherent Interconnect (CCI) uses the software devfreq module
+ to scale the clock frequency and adjust the voltage. MediaTek CCI shares
+ the same power supplies with CPU, so the scheduling involves with CPUfreq.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8183-cci
+ - mediatek,mt8186-cci
+
+ clocks:
+ items:
+ - description:
+ The multiplexer for clock input of CPU cluster.
+ - description:
+ A parent of "cpu" clock which is used as an intermediate clock source
+ when the original CPU is under transition and not stable yet.
+
+ clock-names:
+ items:
+ - const: cci
+ - const: intermediate
+
+ operating-points-v2:
+ description:
+ For details, please refer to
+ Documentation/devicetree/bindings/opp/opp-v2.yaml
+
+ proc-supply:
+ description:
+ Phandle of the regulator for CCI that provides the supply voltage.
+
+ sram-supply:
+ description:
+ Phandle of the regulator for sram of CCI that provides the supply
+ voltage. When it presents, the cci devfreq driver needs to do
+ "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
+ SoC specific needs. When absent, the voltage scaling flow is handled by
+ hardware, hence no software "voltage tracking" is needed.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - operating-points-v2
+ - proc-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ proc-supply = <&mt6358_vproc12_reg>;
+ };
--
2.18.0
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