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Date: Fri, 8 Apr 2022 11:00:30 +0300 From: Claudiu Beznea <claudiu.beznea@...rochip.com> To: <robh+dt@...nel.org>, <nicolas.ferre@...rochip.com>, <alexandre.belloni@...tlin.com>, <p.zabel@...gutronix.de>, <linux@...linux.org.uk>, <sre@...nel.org>, <linux-arm-kernel@...ts.infradead.org> CC: <cristian.birsan@...rochip.com>, <linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>, Claudiu Beznea <claudiu.beznea@...rochip.com> Subject: [PATCH v3 09/10] ARM: dts: at91: sama7g5: add reset-controller node Add reset controller node. Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com> --- arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index eddcfbf4d223..aa0e72d4d2d5 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -122,6 +122,13 @@ pmc: pmc@...18000 { clock-names = "td_slck", "md_slck", "main_xtal"; }; + reset_controller: reset-controller@...1d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + shdwc: shdwc@...1d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; -- 2.32.0
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