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Message-Id: <164941220567.21822.2763856506631523192.b4-ty@arm.com>
Date:   Fri,  8 Apr 2022 11:03:39 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        bhelgaas@...gle.com
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        bjorn.andersson@...aro.org, robh@...nel.org,
        linux-pci@...r.kernel.org, svarbanov@...sol.com
Subject: Re: [PATCH] PCI: qcom: Add support for handling MSIs from 8 endpoints

On Tue, 14 Dec 2021 15:43:19 +0530, Manivannan Sadhasivam wrote:
> The DWC controller used in the Qcom Platforms are capable of addressing the
> MSIs generated from 8 different endpoints each with 32 vectors (256 in
> total). Currently the driver is using the default value of addressing the
> MSIs from 1 endpoint only. Extend it by passing the MAX_MSI_IRQS to the
> num_vectors field of pcie_port structure.
> 
> 
> [...]

Applied to pci/qcom, thanks!

[1/1] PCI: qcom: Add support for handling MSIs from 8 endpoints
      https://git.kernel.org/lpieralisi/pci/c/20f1bfb8dd

Thanks,
Lorenzo

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