linux-kernel - Re: [PATCH 11/11] arm64: dts: Add Pensando Elba SoC support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <87tub21uoz.wl-maz@kernel.org>
Date:   Sat, 09 Apr 2022 10:18:20 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Brad Larson <brad@...sando.io>
Cc:     Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Arnd Bergmann <arnd@...db.de>,
        Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Mark Brown <broonie@...nel.org>,
        Serge Semin <fancer.lancer@...il.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Olof Johansson <olof@...om.net>,
        David Clear <dac2@...sando.io>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        linux-spi <linux-spi@...r.kernel.org>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 11/11] arm64: dts: Add Pensando Elba SoC support

On Sat, 09 Apr 2022 03:38:55 +0100,
Brad Larson <brad@...sando.io> wrote:
> 
> On Thu, Apr 7, 2022 at 12:57 AM Marc Zyngier <maz@...nel.org> wrote:
> >
> > > +             gic: interrupt-controller@...000 {
> > > +                     compatible = "arm,gic-v3";
> > > +                     #interrupt-cells = <3>;
> > > +                     #address-cells = <2>;
> > > +                     #size-cells = <2>;
> > > +                     ranges;
> > > +                     interrupt-controller;
> > > +                     reg = <0x0 0x800000 0x0 0x200000>,      /* GICD */
> > > +                           <0x0 0xa00000 0x0 0x200000>;      /* GICR */
> >
> > You are still missing the GICV and GICH regions that are
> > provided by the CPU. I already pointed that out in [1].
> >
> > The Cortex-A72 TRM will tell you where to find them (at
> > an offset from PERIPHBASE).
> 
> Hi Marc,
> 
> Got the addresses, neither region is used, and will be included in the
> next submission.

Not sure what you mean by these regions being unused here (the Linux
kernel definitely makes use of them). Note that you'll also need to
add GICC (which I forgot to mention above).

	M.

-- 
Without deviation from the norm, progress is not possible.