linux-kernel - [PATCH v14 4/6] dt-bindings: soc: mediatek: add gce-client-reg for MUTEX

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220411072403.24016-5-moudy.ho@mediatek.com>
Date:   Mon, 11 Apr 2022 15:24:01 +0800
From:   Moudy Ho <moudy.ho@...iatek.com>
To:     Mauro Carvalho Chehab <mchehab@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Hans Verkuil <hverkuil-cisco@...all.nl>,
        Jernej Skrabec <jernej.skrabec@...l.net>
CC:     Chun-Kuang Hu <chunkuang.hu@...nel.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Rob Landley <rob@...dley.net>,
        Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        <linux-media@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        Alexandre Courbot <acourbot@...omium.org>,
        <tfiga@...omium.org>, <drinkcat@...omium.org>,
        <pihsun@...omium.org>, <hsinyi@...gle.com>,
        "Benjamin Gaignard" <benjamin.gaignard@...labora.com>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        daoyuan huang <daoyuan.huang@...iatek.com>,
        Ping-Hsun Wu <ping-hsun.wu@...iatek.com>,
        <allen-kh.cheng@...iatek.com>, <xiandong.wang@...iatek.com>,
        <randy.wu@...iatek.com>, <moudy.ho@...iatek.com>,
        <jason-jh.lin@...iatek.com>, <roy-cw.yeh@...iatek.com>,
        <river.cheng@...iatek.com>, <srv_heupstream@...iatek.com>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH v14 4/6] dt-bindings: soc: mediatek: add gce-client-reg for MUTEX

In order to allow modules with latency requirements such as MDP3
to set registers through CMDQ, add the relevant GCE property.

Signed-off-by: Moudy Ho <moudy.ho@...iatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: CK Hu <ck.hu@...iatek.com>
---
 .../bindings/soc/mediatek/mediatek,mutex.yaml        | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index 40598243c84d..e4399e1f9b1c 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -60,6 +60,18 @@ properties:
       include/dt-bindings/gce/<chip>-gce.h of each chips.
     $ref: /schemas/types.yaml#/definitions/uint32-array
 
+  mediatek,gce-client-reg:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: phandle of GCE
+        - description: GCE subsys id
+        - description: register offset
+        - description: register size
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property. Each GCE subsys id is mapping to
+      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
 required:
   - compatible
   - reg
-- 
2.18.0