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Message-ID: <20220411073124.GC24975@thinkpad>
Date: Mon, 11 Apr 2022 13:01:24 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Rohit Agarwal <quic_rohiagar@...cinc.com>
Cc: will@...nel.org, robin.murphy@....com, joro@...tes.org,
robh+dt@...nel.org, krzk+dt@...nel.org, ulf.hansson@...aro.org,
agross@...nel.org, bjorn.andersson@...aro.org,
linux-arm-kernel@...ts.infradead.org,
iommu@...ts.linux-foundation.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-mmc@...r.kernel.org,
linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI
controller
On Mon, Apr 11, 2022 at 12:25:39PM +0530, Rohit Agarwal wrote:
> Add devicetree support for SDHCI controller found in Qualcomm SDX65
> platform. The SDHCI controller is based on the MSM SDHCI v5 IP.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Thanks,
Mani
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 365df74..632ac78 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -168,6 +168,19 @@
> #interrupt-cells = <2>;
> };
>
> + sdhc_1: sdhci@...4000 {
> + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x08804000 0x1000>;
> + reg-names = "hc_mem";
> + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> + clocks = <&gcc GCC_SDCC1_APPS_CLK>,
> + <&gcc GCC_SDCC1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> pdc: interrupt-controller@...0000 {
> compatible = "qcom,sdx65-pdc", "qcom,pdc";
> reg = <0xb210000 0x10000>;
> --
> 2.7.4
>
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