linux-kernel - Re: [PATCH v4, 1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11

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Message-ID: <54c2b102-1506-cdda-51b6-39823d17134c@collabora.com>
Date:   Mon, 11 Apr 2022 11:07:31 +0200
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     xinlei.lee@...iatek.com, chunkuang.hu@...nel.org,
        p.zabel@...gutronix.de, airlied@...ux.ie, daniel@...ll.ch,
        matthias.bgg@...il.com, rex-bc.chen@...iatek.com
Cc:     dri-devel@...ts.freedesktop.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, jitao.shi@...iatek.com,
        Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v4, 1/4] drm/mediatek: Adjust the timing of mipi signal
 from LP00 to LP11

Il 11/04/22 04:31, xinlei.lee@...iatek.com ha scritto:
> From: Jitao Shi <jitao.shi@...iatek.com>
> 
> Old sequence:
> 1. Pull the MIPI signal high
> 2. Delay & Dsi_reset
> 3. Set the dsi timing register
> 4. dsi clk & lanes leave ulp mode and enter hs mode
> 
> The sequence after patching is:
> 1. Set the dsi timing register
> 2. Pull the MIPI signal high
> 3. Delay & Dsi_reset
> 4. dsi clk & lanes leave ulp mode and enter hs mode
> 
> Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API")
> 
> Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
> Signed-off-by: Xinlei Lee <xinlei.lee@...iatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>