linux-kernel - Re: [PATCH] csky: cmpxchg: Optimize with acquire & release

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Message-ID: <YlP27GT05DdyFjlY@FVFF77S0Q05N>
Date:   Mon, 11 Apr 2022 10:37:48 +0100
From:   Mark Rutland <mark.rutland@....com>
To:     guoren@...nel.org
Cc:     arnd@...db.de, peterz@...radead.org, linux-csky@...r.kernel.org,
        linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
        Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH] csky: cmpxchg: Optimize with acquire & release

Hi Guo,

On Wed, Apr 06, 2022 at 08:40:56PM +0800, guoren@...nel.org wrote:
> From: Guo Ren <guoren@...ux.alibaba.com>
> 
> Optimize arch_xchg|cmpxchg|cmpxchg_local with  ASM acquire|release
> instructions instead of previous C based.
> 
> Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@...nel.org>
> ---
>  arch/csky/include/asm/barrier.h |   8 +-
>  arch/csky/include/asm/cmpxchg.h | 173 ++++++++++++++++++++++++++++++--
>  2 files changed, 172 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/csky/include/asm/barrier.h b/arch/csky/include/asm/barrier.h
> index f4045dd53e17..a075f17d02dd 100644
> --- a/arch/csky/include/asm/barrier.h
> +++ b/arch/csky/include/asm/barrier.h
> @@ -37,6 +37,9 @@
>   * bar.brar
>   * bar.bwaw
>   */
> +#define ACQUIRE_FENCE		".long 0x8427c000\n"
> +#define RELEASE_FENCE		".long 0x842ec000\n"

[...]

> +#define __xchg(new, ptr, size)					\
> +({								\
> +	__typeof__(ptr) __ptr = (ptr);				\
> +	__typeof__(new) __new = (new);				\
> +	__typeof__(*(ptr)) __ret;				\
> +	unsigned long tmp;					\
> +	switch (size) {						\
> +	case 4:							\
> +		asm volatile (					\
> +		"1:	ldex.w		%0, (%3) \n"		\
> +		ACQUIRE_FENCE					\
> +		"	mov		%1, %2   \n"		\
> +		RELEASE_FENCE					\
> +		"	stex.w		%1, (%3) \n"		\
> +		"	bez		%1, 1b   \n"		\
> +			: "=&r" (__ret), "=&r" (tmp)		\
> +			: "r" (__new), "r"(__ptr)		\
> +			:);					\

As with the riscv case, I believe this suffers the problem described in:

  8e86f0b409a44193 ("arm64: atomics: fix use of acquire + release for full barrier semantics")

... and does not provide FULL ordering semantics.

[...]

> +#define __cmpxchg(ptr, old, new, size)				\
> +({								\
> +	__typeof__(ptr) __ptr = (ptr);				\
> +	__typeof__(new) __new = (new);				\
> +	__typeof__(new) __tmp;					\
> +	__typeof__(old) __old = (old);				\
> +	__typeof__(*(ptr)) __ret;				\
> +	switch (size) {						\
> +	case 4:							\
> +		asm volatile (					\
> +		"1:	ldex.w		%0, (%3) \n"		\
> +		ACQUIRE_FENCE					\
> +		"	cmpne		%0, %4   \n"		\
> +		"	bt		2f       \n"		\
> +		"	mov		%1, %2   \n"		\
> +		RELEASE_FENCE					\
> +		"	stex.w		%1, (%3) \n"		\
> +		"	bez		%1, 1b   \n"		\
> +		"2:				 \n"		\
> +			: "=&r" (__ret), "=&r" (__tmp)		\
> +			: "r" (__new), "r"(__ptr), "r"(__old)	\
> +			:);					\

Likewise.

Thanks,
Mark.