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Message-ID: <YlP3ngtgfaQeq5Q9@FVFF77S0Q05N> Date: Mon, 11 Apr 2022 10:40:46 +0100 From: Mark Rutland <mark.rutland@....com> To: guoren@...nel.org Cc: arnd@...db.de, peterz@...radead.org, linux-csky@...r.kernel.org, linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org, Guo Ren <guoren@...ux.alibaba.com> Subject: Re: [PATCH] csky: atomic: Add custom atomic.h implementation On Wed, Apr 06, 2022 at 08:54:36PM +0800, guoren@...nel.org wrote: > From: Guo Ren <guoren@...ux.alibaba.com> > > The generic atomic.h used cmpxchg to implement the atomic > operations, it will cause daul loop to reduce the forward > guarantee. The patch implement csky custom atomic operations with > ldex/stex instructions for the best performance. > > Signed-off-by: Guo Ren <guoren@...ux.alibaba.com> > Signed-off-by: Guo Ren <guoren@...nel.org> > --- > arch/csky/include/asm/atomic.h | 251 +++++++++++++++++++++++++++++++++ > 1 file changed, 251 insertions(+) > create mode 100644 arch/csky/include/asm/atomic.h > +static __always_inline \ > +int arch_atomic_fetch_##op(int i, atomic_t *v) \ > +{ \ > + register int ret, tmp; \ > + __asm__ __volatile__ ( \ > + "1: ldex.w %0, (%3) \n" \ > + ACQUIRE_FENCE \ > + " mov %1, %0 \n" \ > + " " #op " %0, %2 \n" \ > + RELEASE_FENCE \ > + " stex.w %0, (%3) \n" \ > + " bez %0, 1b \n" \ > + : "=&r" (tmp), "=&r" (ret) \ > + : "r" (I), "r"(&v->counter) \ > + : "memory"); \ > + return ret; \ > +} I believe this suffers the problem described in: 8e86f0b409a44193 ("arm64: atomics: fix use of acquire + release for full barrier semantics") ... and does not provide FULL ordering semantics. Thanks, Mark.
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