linux-kernel - [PATCH v2 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <1649670615-21268-4-git-send-email-quic_rohiagar@quicinc.com>
Date:   Mon, 11 Apr 2022 15:20:11 +0530
From:   Rohit Agarwal <quic_rohiagar@...cinc.com>
To:     will@...nel.org, robin.murphy@....com, joro@...tes.org,
        robh+dt@...nel.org, krzk+dt@...nel.org, ulf.hansson@...aro.org,
        agross@...nel.org, bjorn.andersson@...aro.org
Cc:     manivannan.sadhasivam@...aro.org,
        linux-arm-kernel@...ts.infradead.org,
        iommu@...ts.linux-foundation.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-mmc@...r.kernel.org,
        linux-arm-msm@...r.kernel.org,
        Rohit Agarwal <quic_rohiagar@...cinc.com>
Subject: [PATCH v2 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller

Add devicetree support for SDHCI controller found in Qualcomm SDX65
platform. The SDHCI controller is based on the MSM SDHCI v5 IP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@...cinc.com>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index dcc94c2..77bca58 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -137,6 +137,19 @@
 			status = "disabled";
 		};
 
+		sdhc_1: sdhci@...4000 {
+			compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
+			reg = <0x08804000 0x1000>;
+			reg-names = "hc_mem";
+			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
+				 <&gcc GCC_SDCC1_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "disabled";
+		};
+
 		spmi_bus: qcom,spmi@...0000 {
 			compatible = "qcom,spmi-pmic-arb";
 			reg = <0xc440000 0xd00>,
-- 
2.7.4