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Message-Id: <20220411105438.21366-1-eric.lin@sifive.com>
Date: Mon, 11 Apr 2022 18:54:37 +0800
From: Eric Lin <eric.lin@...ive.com>
To: peterz@...radead.org, mingo@...hat.com, acme@...nel.org,
mark.rutland@....com, alexander.shishkin@...ux.intel.com,
jolsa@...nel.org, namhyung@...nel.org, palmer@...belt.com,
aou@...s.berkeley.edu, iii@...ux.ibm.com,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org
Cc: paul.walmsley@...ive.com, Eric Lin <eric.lin@...ive.com>
Subject: [PATCH v2 0/1] perf jitdump: Add riscv64 support
This patch enable perf jitdump for riscv64 and it tested with V8 on qemu rv64.
Qemu rv64:
$ perf record -e cpu-clock -c 1000 -g -k mono ./d8_rv64 --perf-prof --no-write-protect-code-memory test.js
$ perf inject -j -i perf.data -o perf.data.jitted
$ perf report -i perf.data.jitted
Output:
To display the perf.data header info, please use --header/--header-only options.
Total Lost Samples: 0
Samples: 87K of event 'cpu-clock'
Event count (approx.): 87974000
Children Self Command Shared Object Symbol
....
0.28% 0.06% d8_rv64 d8_rv64 [.] _ZN2v88i
nternal6WasmJs7InstallEPNS0_7IsolateEb
0.28% 0.00% d8_rv64 d8_rv64 [.] _ZN2v88i
nternal10ParserBaseINS0_6ParserEE22ParseLogicalExpressionEv
0.28% 0.03% d8_rv64 jitted-112-76.so [.] Builtin:
InterpreterEntryTrampoline
0.12% 0.00% d8_rv64 d8_rv64 [.] _ZN2v88i
nternal19ContextDeserializer11DeserializeEPNS0_7IsolateENS0_6HandleINS0_13JSGlob
alProxyEEENS_33DeserializeInternalFieldsCallbackE
0.12% 0.01% d8_rv64 jitted-112-651.so [.] Builtin:
CEntry_Return1_DontSaveFPRegs_ArgvOnStack_NoBuiltinExit
....
Changed in v2:
- Rebase on tag v5.18-rc2
- Show perf jitdump commands and dump in the commit message.
Eric Lin (1):
perf jitdump: Add riscv64 support.
tools/perf/arch/riscv/Makefile | 1 +
tools/perf/util/genelf.h | 3 +++
2 files changed, 4 insertions(+)
--
2.35.1
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