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Date: Tue, 12 Apr 2022 11:17:04 +0100 From: Mike Leach <mike.leach@...aro.org> To: James Clark <James.Clark@....com> Cc: suzuki.poulose@....com, coresight@...ts.linaro.org, Anshuman.Khandual@....com, mathieu.poirier@...aro.org, leo.yan@...aro.com, Leo Yan <leo.yan@...aro.org>, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH v3 10/15] coresight: etm3x: Cleanup ETMTECR1 register accesses On Fri, 4 Mar 2022 at 17:19, James Clark <james.clark@....com> wrote: > > This is a no-op change for style and consistency and has no effect on > the binary output by the compiler. These fields already have macros > to define them so use them instead of magic numbers. > > Signed-off-by: James Clark <james.clark@....com> > --- > drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 +- > drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > index 7d413ba8b823..d0ab9933472b 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > @@ -204,7 +204,7 @@ void etm_set_default(struct etm_config *config) > * set all bits in register 0x007, the ETMTECR2, to 0 > * set register 0x008, the ETMTEEVR, to 0x6F (TRUE). > */ > - config->enable_ctrl1 = BIT(24); > + config->enable_ctrl1 = ETMTECR1_INC_EXC; > config->enable_ctrl2 = 0x0; > config->enable_event = ETM_HARD_WIRE_RES_A; > > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c > index e8c7649f123e..68fcbf4ce7a8 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c > @@ -474,7 +474,7 @@ static ssize_t addr_start_store(struct device *dev, > config->addr_val[idx] = val; > config->addr_type[idx] = ETM_ADDR_TYPE_START; > config->startstop_ctrl |= (1 << idx); > - config->enable_ctrl1 |= BIT(25); > + config->enable_ctrl1 |= ETMTECR1_START_STOP; > spin_unlock(&drvdata->spinlock); > > return size; > -- > 2.28.0 > Reviewed-by: Mike Leach <mike.leach@...aro.org> -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK
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