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Message-ID: <c8f9c4a6-9fdb-7d84-6416-c64943acb966@microchip.com>
Date: Tue, 12 Apr 2022 10:43:06 +0000
From: <Tudor.Ambarus@...rochip.com>
To: <krzysztof.kozlowski@...aro.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <Nicolas.Ferre@...rochip.com>,
<alexandre.belloni@...tlin.com>, <Claudiu.Beznea@...rochip.com>,
<Lars.Povlsen@...rochip.com>, <Steen.Hegelund@...rochip.com>,
<UNGLinuxDriver@...rochip.com>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] arm64: dts: microchip: align SPI NOR node name with
dtschema
On 4/7/22 17:32, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> The node names should be generic and SPI NOR dtschema expects "flash".
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@...rochip.com>
> ---
> arch/arm64/boot/dts/microchip/sparx5_nand.dtsi | 2 +-
> arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 4 ++--
> arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 4 ++--
> arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 4 ++--
> 4 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
> index 03f107e427d7..ce0747fd6444 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
> @@ -19,7 +19,7 @@ spi@e {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <14>; /* CS14 */
> - spi-flash@6 {
> + flash@6 {
> compatible = "spi-nand";
> pinctrl-0 = <&cs14_pins>;
> pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
> index 9baa085d7861..dbf8c1d48a02 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
> +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
> @@ -47,7 +47,7 @@ spi@0 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0>; /* CS0 */
> - spi-flash@9 {
> + flash@9 {
> compatible = "jedec,spi-nor";
> spi-max-frequency = <8000000>;
> reg = <0x9>; /* SPI */
> @@ -59,7 +59,7 @@ spi@1 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <1>; /* CS1 */
> - spi-flash@9 {
> + flash@9 {
> compatible = "spi-nand";
> pinctrl-0 = <&cs1_pins>;
> pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
> index 33faf1f3264f..699256f1b9d8 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
> @@ -274,7 +274,7 @@ gpio@1 {
>
> &spi0 {
> status = "okay";
> - spi-flash@0 {
> + flash@0 {
> compatible = "jedec,spi-nor";
> spi-max-frequency = <8000000>;
> reg = <0>;
> @@ -289,7 +289,7 @@ spi@0 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0>; /* CS0 */
> - spi-flash@9 {
> + flash@9 {
> compatible = "jedec,spi-nor";
> spi-max-frequency = <8000000>;
> reg = <0x9>; /* SPI */
> diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
> index ef96e6d8c6b3..d10a9172b529 100644
> --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
> +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
> @@ -89,7 +89,7 @@ i2cmux_s32: i2cmux-3 {
>
> &spi0 {
> status = "okay";
> - spi-flash@0 {
> + flash@0 {
> compatible = "jedec,spi-nor";
> spi-max-frequency = <8000000>;
> reg = <0>;
> @@ -104,7 +104,7 @@ spi@0 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0>; /* CS0 */
> - spi-flash@9 {
> + flash@9 {
> compatible = "jedec,spi-nor";
> spi-max-frequency = <8000000>;
> reg = <0x9>; /* SPI */
> --
> 2.32.0
>
>
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> linux-arm-kernel mailing list
> linux-arm-kernel@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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