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Message-Id: <20220412190817.125886-1-pgwipeout@gmail.com>
Date: Tue, 12 Apr 2022 15:08:17 -0400
From: Peter Geis <pgwipeout@...il.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>
Cc: linux-rockchip@...ts.infradead.org,
Peter Geis <pgwipeout@...il.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH] arm64: dts: rockchip: add rk356x sfc support
Add the sfc node to the rk356x device tree.
The sfc node on rk356x can function as a boot device and supports four
lanes of receive data and one lane of transmit data for supported
SPI-NOR chips.
Signed-off-by: Peter Geis <pgwipeout@...il.com>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index d5131f5aaf73..b52edcdbbe7d 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -812,6 +812,17 @@ sdmmc1: mmc@...c0000 {
status = "disabled";
};
+ sfc: spi@...00000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe300000 0x0 0x4000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
sdhci: mmc@...10000 {
compatible = "rockchip,rk3568-dwcmshc";
reg = <0x0 0xfe310000 0x0 0x10000>;
--
2.25.1
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