linux-kernel - RE: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <DU2PR04MB894975813DAC1043AAA23C5B8FEC9@DU2PR04MB8949.eurprd04.prod.outlook.com>
Date:   Wed, 13 Apr 2022 18:03:37 +0000
From:   Leo Li <leoyang.li@....com>
To:     Vladimir Oltean <olteanv@...il.com>,
        "Z.Q. Hou" <zhiqiang.hou@....com>
CC:     Shawn Guo <shawnguo@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Xiaowei Bao <xiaowei.bao@....com>
Subject: RE: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes



> -----Original Message-----
> From: Vladimir Oltean <olteanv@...il.com>
> Sent: Wednesday, April 13, 2022 11:32 AM
> To: Leo Li <leoyang.li@....com>
> Cc: Shawn Guo <shawnguo@...nel.org>; linux-arm-
> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; Xiaowei Bao
> <xiaowei.bao@....com>
> Subject: Re: [PATCH v3 1/8] arm64: dts: ls1028a: Add PCIe EP nodes
> 
> On Tue, Dec 14, 2021 at 03:32:33AM -0600, Li Yang wrote:
> > From: Xiaowei Bao <xiaowei.bao@....com>
> >
> > Add PCIe EP nodes for ls1028a to support EP mode.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
> > Signed-off-by: Li Yang <leoyang.li@....com>
> > ---
> >  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24
> > +++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index fd3f3e8bb6ce..9010c535252a 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -637,6 +637,18 @@ pcie1: pcie@...0000 {
> >  			status = "disabled";
> >  		};
> >
> > +		pcie_ep1: pcie-ep@...0000 {
> > +			compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> > +			reg = <0x00 0x03400000 0x0 0x00100000
> > +			       0x80 0x00000000 0x8 0x00000000>;
> > +			reg-names = "regs", "addr_space";
> > +			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> /* PME interrupt */
> > +			interrupt-names = "pme";
> > +			num-ib-windows = <6>;
> > +			num-ob-windows = <8>;
> > +			status = "disabled";
> > +		};
> > +
> >  		pcie2: pcie@...0000 {
> >  			compatible = "fsl,ls1028a-pcie";
> >  			reg = <0x00 0x03500000 0x0 0x00100000>, /*
> controller registers */
> > @@ -664,6 +676,18 @@ pcie2: pcie@...0000 {
> >  			status = "disabled";
> >  		};
> >
> > +		pcie_ep2: pcie-ep@...0000 {
> > +			compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> > +			reg = <0x00 0x03500000 0x0 0x00100000
> > +			       0x88 0x00000000 0x8 0x00000000>;
> > +			reg-names = "regs", "addr_space";
> > +			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> /* PME interrupt */
> > +			interrupt-names = "pme";
> > +			num-ib-windows = <6>;
> > +			num-ob-windows = <8>;
> > +			status = "disabled";
> > +		};
> > +
> >  		smmu: iommu@...0000 {
> >  			compatible = "arm,mmu-500";
> >  			reg = <0 0x5000000 0 0x800000>;
> > --
> > 2.25.1
> >
> 
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:631.23-656.5: Warning
> (unique_unit_address): /soc/pcie@...0000: duplicate unit-address (also
> used in node /soc/pcie-ep@...0000)
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi:670.23-695.5: Warning
> (unique_unit_address): /soc/pcie@...0000: duplicate unit-address (also
> used in node /soc/pcie-ep@...0000)

This would be a common problem for all the layerscape PCIe controller.  The controller can either work in RC mode or EP mode.  The current binding of the controller defined two compatibles, one for RC and one for EP.  Therefore the SoC dtsi will have two nodes with the same unit address one for EP one for RC.  Fixing this probably requires comprehensive updates to the binding which breaks backward compatibility.

Regards,
Leo