linux-kernel - Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver

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Date:   Wed, 13 Apr 2022 12:15:01 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Krzysztof Kozlowski <krzk@...nel.org>
Cc:     wangseok.lee@...sung.com,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
        "kishon@...com" <kishon@...com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "jesper.nilsson@...s.com" <jesper.nilsson@...s.com>,
        "lars.persson@...s.com" <lars.persson@...s.com>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "kw@...ux.com" <kw@...ux.com>,
        "linux-arm-kernel@...s.com" <linux-arm-kernel@...s.com>,
        "kernel@...s.com" <kernel@...s.com>,
        전문기 <moonki.jun@...sung.com>
Subject: Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver

On 28-03-22, 13:40, Krzysztof Kozlowski wrote:
> On 28/03/2022 13:29, 이왕석 wrote:
> >> --------- Original Message ---------
> >> Sender : Krzysztof Kozlowski <krzk@...nel.org>
> >> Date : 2022-03-28 18:38 (GMT+9)
> >> Title : Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver
> >>
> >> On 28/03/2022 11:02, 이왕석 wrote:
> >>>>  --------- Original Message ---------
> >>>>  Sender : Krzysztof Kozlowski <krzk@...nel.org>
> >>>>  Date : 2022-03-28 16:12 (GMT+9)
> >>>>  Title : Re: [PATCH 0/5] Add support for Axis, ARTPEC-8 PCIe driver
> >>>>
> >>>>  On 28/03/2022 03:44, 이왕석 wrote:
> >>>>>   This series patches include newly PCIe support for Axis ARTPEC-8 SoC.
> >>>>>   ARTPEC-8 is the SoC platform of Axis Communications.
> >>>>>   PCIe controller driver and phy driver have been newly added.
> >>>>>   There is also a new MAINTAINER in the addition of phy driver.
> >>>>>   PCIe controller is designed based on Design-Ware PCIe controller IP
> >>>>>   and PCIe phy is desinged based on SAMSUNG PHY IP.
> >>>>>   It also includes modifications to the Design-Ware controller driver to 
> >>>>>   run the 64bit-based ARTPEC-8 PCIe controller driver.
> >>>>>   It consists of 6 patches in total.
> >>>>>   
> >>>>>   This series has been tested on AXIS SW bring-up board 
> >>>>>   with ARTPEC-8 chipset.
> >>>>
> >>>>  You lost mail threading. This makes reading this difficult for us. Plus
> >>>>  you sent something non-applicable (patch #2), so please resend.
> >>>>
> >>>>  Knowing recent Samsung reluctance to extend existing drivers and always
> >>>>  duplicate, please provide description/analysis why this driver cannot be
> >>>>  combined with existing driver. The answer like: we need several syscon
> >>>>  because we do not implement other frameworks (like interconnect) are not
> >>>>  valid.
> >>>>
> >>>>  Best regards,
> >>>>  Krzysztof
> >>>  
> >>>  Hello, Krzysztof
> >>>  Thanks for your review.
> >>>  
> >>>  patch#2 was sent to the wrong format so sent again.
> >>>  Sorry for causing confusion.
> >>  
> >> The first sending was HTML. Second was broken text, so still not working.
> >>
> >> Please resend everything with proper threading.
> > 
> > Hello, Krzysztof
> > 
> > I sent patch#2 three times.
> > due to the influence of the email system,
> > there was something wrong with the first and second mails.
> > Sorry for causing confusion.
> > Did you receive the third patch i sent you?
> 
> Maybe, I don't know. It's not threaded so it's difficult to find it
> among other 100 emails...

Correct, this is spread over whole list, please resend the whole series
in a single shot without threading being broken

-- 
~Vinod