linux-kernel - Re: [PATCH v9 09/12] riscv: add RISC-V Svpbmt extension support

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Date:   Wed, 13 Apr 2022 11:11:09 +0200
From:   Philipp Tomsich <philipp.tomsich@...ll.eu>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     palmer@...belt.com, paul.walmsley@...ive.com,
        aou@...s.berkeley.edu, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, wefu@...hat.com,
        liush@...winnertech.com, guoren@...nel.org, atishp@...shpatra.org,
        anup@...infault.org, drew@...gleboard.org, hch@....de,
        arnd@...db.de, wens@...e.org, maxime@...no.tech,
        gfavor@...tanamicro.com, andrea.mondelli@...wei.com,
        behrensj@....edu, xinhaoqu@...wei.com, mick@....forth.gr,
        allen.baum@...erantotech.com, jscheid@...tanamicro.com,
        rtrauben@...il.com, samuel@...lland.org, cmuellner@...ux.com,
        Wei Wu <lazyparser@...il.com>,
        Daniel Lustig <dlustig@...dia.com>,
        Bill Huffman <huffman@...ence.com>
Subject: Re: [PATCH v9 09/12] riscv: add RISC-V Svpbmt extension support

On Wed, 13 Apr 2022 at 05:03, Heiko Stuebner <heiko@...ech.de> wrote:
>
> Svpbmt (the S should be capitalized) is the
> "Supervisor-mode: page-based memory types" extension
> that specifies attributes for cacheability, idempotency
> and ordering.
>
> The relevant settings are done in special bits in PTEs:
>
> Here is the svpbmt PTE format:
> | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
>   N     MT     RSW    D   A   G   U   X   W   R   V
>         ^
>
> Of the Reserved bits [63:54] in a leaf PTE, the high bit is already
> allocated (as the N bit), so bits [62:61] are used as the MT (aka
> MemType) field. This field specifies one of three memory types that
> are close equivalents (or equivalent in effect) to the three main x86
> and ARMv8 memory types - as shown in the following table.
>
> RISC-V
> Encoding &
> MemType     RISC-V Description
> ----------  ------------------------------------------------
> 00 - PMA    Normal Cacheable, No change to implied PMA memory type
> 01 - NC     Non-cacheable, idempotent, weakly-ordered Main Memory
> 10 - IO     Non-cacheable, non-idempotent, strongly-ordered I/O memory
> 11 - Rsvd   Reserved for future standard use
>
> As the extension will not be present on all implementations,
> implement a method to handle cpufeatures via alternatives
> to not incur runtime penalties on cpu variants not supporting
> specific extensions and patch relevant code parts at runtime.
>
> Co-developed-by: Wei Fu <wefu@...hat.com>
> Signed-off-by: Wei Fu <wefu@...hat.com>
> Co-developed-by: Liu Shaohua <liush@...winnertech.com>
> Signed-off-by: Liu Shaohua <liush@...winnertech.com>
> Co-developed-by: Guo Ren <guoren@...nel.org>
> Signed-off-by: Guo Ren <guoren@...nel.org>
> [moved to use the alternatives mechanism]
> Signed-off-by: Heiko Stuebner <heiko@...ech.de>
> Cc: Christoph Hellwig <hch@....de>
> Cc: Arnd Bergmann <arnd@...db.de>
> Cc: Drew Fustini <drew@...gleboard.org>
> Cc: Wei Fu <wefu@...hat.com>
> Cc: Wei Wu <lazyparser@...il.com>
> Cc: Chen-Yu Tsai <wens@...e.org>
> Cc: Maxime Ripard <maxime@...no.tech>
> Cc: Daniel Lustig <dlustig@...dia.com>
> Cc: Greg Favor <gfavor@...tanamicro.com>
> Cc: Andrea Mondelli <andrea.mondelli@...wei.com>
> Cc: Jonathan Behrens <behrensj@....edu>
> Cc: Xinhaoqu (Freddie) <xinhaoqu@...wei.com>
> Cc: Bill Huffman <huffman@...ence.com>
> Cc: Nick Kossifidis <mick@....forth.gr>
> Cc: Allen Baum <allen.baum@...erantotech.com>
> Cc: Josh Scheid <jscheid@...tanamicro.com>
> Cc: Richard Trauben <rtrauben@...il.com>

Reviewed-by: Philipp Tomsich <philipp.tomsich@...ll.eu>