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Message-ID: <534dbd19-b43b-63e6-69e0-3441dd224ef0@nvidia.com>
Date: Thu, 14 Apr 2022 11:01:44 +0530
From: Ashish Mhetre <amhetre@...dia.com>
To: Dmitry Osipenko <dmitry.osipenko@...labora.com>, digetx@...il.com,
krzysztof.kozlowski@...aro.org, thierry.reding@...il.com,
jonathanh@...dia.com, robh+dt@...nel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, krzysztof.kozlowski+dt@...aro.org
Cc: vdumpa@...dia.com, Snikam@...dia.com
Subject: Re: [Patch v7 2/4] memory: tegra: Add MC error logging on tegra186
onward
On 4/14/2022 2:43 AM, Dmitry Osipenko wrote:
> External email: Use caution opening links or attachments
>
>
> On 4/13/22 12:40, Ashish Mhetre wrote:
>> +irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
>> {
>> struct tegra_mc *mc = data;
>> + unsigned int bit, channel;
>> unsigned long status;
>> - unsigned int bit;
>>
>> - /* mask all interrupts to avoid flooding */
>> - status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
>> + if (mc->soc->num_channels) {
>> + u32 global_status;
>> + int err;
>> +
>> + global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS);
>
> This will crash if mc->bcast_ch_regs = ERR_PTR(-EINVAL) for older dtbs.
Actually interrupts won't occur till we write MC_INTMASK register from
broadcast channel with appropriate intmask value. I have added check in
tegra_mc_probe() while registering irq which will write MC_INTMASK from
broadcast only when mc->bcast_ch_regs is initialized i.e.
!IS_ERR(mc->bcast_ch_regs).
So interrupt handler won't be triggered at all if
mc->bcast_ch_regs = ERR_PTR(-EINVAL).
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