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Message-ID: <BL1PR12MB5157EDDA43968B19B5051780E2EF9@BL1PR12MB5157.namprd12.prod.outlook.com>
Date: Thu, 14 Apr 2022 21:06:40 +0000
From: "Limonciello, Mario" <Mario.Limonciello@....com>
To: Dave Hansen <dave.hansen@...el.com>,
Thomas Gleixner <tglx@...utronix.de>,
Peter Zijlstra <peterz@...radead.org>,
"Karny, Wyes" <Wyes.Karny@....com>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"Carroll, Lewis" <Lewis.Carroll@....com>,
"Shenoy, Gautham Ranjal" <gautham.shenoy@....com>,
"Narayan, Ananth" <Ananth.Narayan@....com>,
"Rao, Bharata Bhasker" <bharata@....com>,
"len.brown@...el.com" <len.brown@...el.com>,
"x86@...nel.org" <x86@...nel.org>,
"mingo@...hat.com" <mingo@...hat.com>,
"bp@...en8.de" <bp@...en8.de>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"hpa@...or.com" <hpa@...or.com>,
"chang.seok.bae@...el.com" <chang.seok.bae@...el.com>,
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"metze@...ba.org" <metze@...ba.org>,
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"mark.rutland@....com" <mark.rutland@....com>
Subject: RE: [PATCH] x86: Prefer MWAIT over HALT on AMD processors
[Public]
> -----Original Message-----
> From: Limonciello, Mario
> Sent: Thursday, April 7, 2022 20:24
> To: Dave Hansen <dave.hansen@...el.com>; Thomas Gleixner
> <tglx@...utronix.de>; Peter Zijlstra <peterz@...radead.org>; Karny, Wyes
> <Wyes.Karny@....com>
> Cc: linux-kernel@...r.kernel.org; Carroll, Lewis <Lewis.Carroll@....com>;
> Shenoy, Gautham Ranjal <gautham.shenoy@....com>; Narayan, Ananth
> <Ananth.Narayan@....com>; Rao, Bharata Bhasker <bharata@....com>;
> len.brown@...el.com; x86@...nel.org; mingo@...hat.com; bp@...en8.de;
> dave.hansen@...ux.intel.com; hpa@...or.com; chang.seok.bae@...el.com;
> keescook@...omium.org; metze@...ba.org;
> zhengqi.arch@...edance.com; mark.rutland@....com
> Subject: RE: [PATCH] x86: Prefer MWAIT over HALT on AMD processors
>
> [Public]
>
> >
> > I don't want to give you too hard of a time on this. But, that's not
> > architecture, that's just telling folks what the implementation is on
> > *one* CPU model. Don't get me wrong: these model-specific docs are
> > great, and I wish Intel published something like that.
> >
> > But, the code as written depends on behavior for *all* of family 0x19:
> >
> > > case 0x17: fallthrough;
> > > case 0x19: init_amd_zn(c); break;
> >
> > So, while the docs for "family 19h model 01h" are *consistent* with this
> > code, there's also nothing preventing the docs for "family 19h model
> > 02h" from breaking this new MWAIT code.
> >
> > Now, AMD is full of smart folks that aren't going out of their way to
> > try and break existing software. But, actual documentation of the
> > *architecture* is really preferable to what we have now. It helps
> > establish a shared hardware/software contract that keeps both sides
> honest.
>
> Point taken. As you're probably aware releasing documentation is never a
> quick
> process, but Lewis and Wyes can take this to the powers that be internally to
> see
> what can be done for the future.
This thread did splinter a bit as it was between speculation control and MWAIT.
So I just wanted to complete the thoughts related to the speculation as that came
up. Having gone back over what is in the outward facing documentation I did want
to share to you that APM volume 2 page 67-70 does include the details
for speculation control and proper architectural discovery of the MSR.
https://www.amd.com/system/files/TechDocs/24593.pdf
>
> >
> > What's missing is something that says:
> >
> > All AMD family 0x17 and 0x19 that enumerate support for MWAIT
> > also support this "early MWAIT" implementation
> >
> > That represents a promise from AMD that this can't break in the future.
> > It both gives us something unambiguous to write code with *and*
> > something to help nudge our hardware and microcode colleagues if they
> > start to do something funny in the future.
> >
> > Just having that in the changelog would be fine, and a genuine
> > improvement over what we have now. Having it one of the
> > model-independent architecture manuals would be even better.
>
> OK... I think the commit message and/or a comment is doable in the short
> term for v2.
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