| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20220414074000.31438-12-pbonzini@redhat.com>
Date: Thu, 14 Apr 2022 03:39:49 -0400
From: Paolo Bonzini <pbonzini@...hat.com>
To: linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Cc: seanjc@...gle.com
Subject: [PATCH 11/22] KVM: x86/mmu: cleanup computation of MMU roles for two-dimensional paging
Inline kvm_calc_mmu_role_common into its sole caller, and simplify it
by removing the computation of unnecessary bits.
Extended bits are unnecessary because page walking uses the CPU role,
and EFER.NX/CR0.WP can be set to one unconditionally---matching the
format of shadow pages rather than the format of guest pages.
The MMU role for two dimensional paging does still depend on the CPU role,
even if only barely so, due to SMM and guest mode; for consistency,
pass it down to kvm_calc_tdp_mmu_root_page_role instead of querying
the vcpu with is_smm or is_guest_mode.
Signed-off-by: Paolo Bonzini <pbonzini@...hat.com>
---
arch/x86/kvm/mmu/mmu.c | 41 +++++++++--------------------------------
1 file changed, 9 insertions(+), 32 deletions(-)
diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 3f712d2de0ed..6c0287d60781 100644
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -4734,34 +4734,6 @@ kvm_calc_cpu_role(struct kvm_vcpu *vcpu, const struct kvm_mmu_role_regs *regs)
return role;
}
-static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
- const struct kvm_mmu_role_regs *regs)
-{
- union kvm_mmu_role role = {0};
-
- role.base.access = ACC_ALL;
- if (____is_cr0_pg(regs)) {
- role.ext.cr0_pg = 1;
- role.base.efer_nx = ____is_efer_nx(regs);
- role.base.cr0_wp = ____is_cr0_wp(regs);
-
- role.ext.cr4_pae = ____is_cr4_pae(regs);
- role.ext.cr4_smep = ____is_cr4_smep(regs);
- role.ext.cr4_smap = ____is_cr4_smap(regs);
- role.ext.cr4_pse = ____is_cr4_pse(regs);
-
- /* PKEY and LA57 are active iff long mode is active. */
- role.ext.cr4_pke = ____is_efer_lma(regs) && ____is_cr4_pke(regs);
- role.ext.cr4_la57 = ____is_efer_lma(regs) && ____is_cr4_la57(regs);
- role.ext.efer_lma = ____is_efer_lma(regs);
- }
- role.base.smm = is_smm(vcpu);
- role.base.guest_mode = is_guest_mode(vcpu);
- role.ext.valid = 1;
-
- return role;
-}
-
static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
{
/* tdp_root_level is architecture forced level, use it if nonzero */
@@ -4777,14 +4749,20 @@ static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
static union kvm_mmu_role
kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu,
- const struct kvm_mmu_role_regs *regs)
+ union kvm_mmu_role cpu_role)
{
- union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, regs);
+ union kvm_mmu_role role = {0};
+ role.base.access = ACC_ALL;
+ role.base.cr0_wp = true;
+ role.base.efer_nx = true;
+ role.base.smm = cpu_role.base.smm;
+ role.base.guest_mode = cpu_role.base.guest_mode;
role.base.ad_disabled = (shadow_accessed_mask == 0);
role.base.level = kvm_mmu_get_tdp_level(vcpu);
role.base.direct = true;
role.base.has_4_byte_gpte = false;
+ role.ext.valid = true;
return role;
}
@@ -4794,8 +4772,7 @@ static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu,
{
struct kvm_mmu *context = &vcpu->arch.root_mmu;
union kvm_mmu_role cpu_role = kvm_calc_cpu_role(vcpu, regs);
- union kvm_mmu_role mmu_role =
- kvm_calc_tdp_mmu_root_page_role(vcpu, regs);
+ union kvm_mmu_role mmu_role = kvm_calc_tdp_mmu_root_page_role(vcpu, cpu_role);
if (cpu_role.as_u64 == context->cpu_role.as_u64 &&
mmu_role.as_u64 == context->mmu_role.as_u64)
--
2.31.1
Powered by blists - more mailing lists