[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3acd20b2-5882-7cc0-8a7b-7b406b768c1c@codethink.co.uk>
Date: Thu, 14 Apr 2022 08:11:00 +0100
From: Ben Dooks <ben.dooks@...ethink.co.uk>
To: "Maciej W. Rozycki" <macro@...am.me.uk>
Cc: Alexandre Ghiti <alex@...ti.fr>, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Bjorn Helgaas <bhelgaas@...gle.com>,
Palmer Dabbelt <palmer@...belt.com>,
Rob Herring <robh@...nel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Greentime Hu <greentime.hu@...ive.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
David Abdurachmanov <david.abdurachmanov@...ive.com>,
Neill Whillans <neill.whillans@...ethink.co.uk>
Subject: Re: [V3] PCI: fu740: Drop to 2.5GT/s to fix initial device probing on
some boards
On 14/04/2022 01:10, Maciej W. Rozycki wrote:
> On Wed, 23 Mar 2022, Ben Dooks wrote:
>
>>> FWIW, I have tested this and it solved my issue with nvme not being probed,
>>> so:
>>>
>>> Tested-by: Alexandre Ghiti <alexandre.ghiti@...onical.com>
>>
>> Ok, great. Our test rig seems to be still working with this.
>
> I ran simple verification of your change by interrupting U-Boot after a
> power-up and issuing:
>
> => setenv boot_pci_enum true
>
> at the command prompt before booting from the uSD card and curiously
> enough the root port comes up with the Link Capabilities Register
> reporting the lack of Link Bandwidth Notification Capability in this
> scenario, while it reports its presence if booted undisturbed, i.e.:
>
> LnkCap: Port #0, Speed 8GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <4us, L1 <4us
> ClockPM- Surprise- LLActRep+ BwNot- ASPMOptComp+
>
> vs:
>
> LnkCap: Port #0, Speed 8GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <4us, L1 <4us
> ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
>
> It is fully reproducible.
>
> Any idea what might be causing it? I can't see it being explicitly set
> or cleared anywhere, be it in U-Boot or Linux, so it must be done by the
> device itself depending on something. And the lack of this capability
> seems to me like non-compliance for a multiple-lane, multiple-speed
> device.
I'll see if we can reproduce this
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
Powered by blists - more mailing lists