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Message-ID: <20220414025023.11516-1-Nick.Fan@mediatek.com>
Date: Thu, 14 Apr 2022 10:50:22 +0800
From: Nick Fan <Nick.Fan@...iatek.com>
To: Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
CC: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>,
<dri-devel@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
<srv_heupstream@...iatek.com>,
<linux-mediatek@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <fshao@...omium.org>,
<wenst@...omium.org>, <alyssa.rosenzweig@...labora.com>,
<nick.fan@...iatek.com>, Nick Fan <Nick.Fan@...iatek.com>
Subject: [PATCH v6 1/2] dt-bindings: Add DT schema for Arm Mali Valhall GPU
Add devicetree schema for Arm Mali Valhall GPU
Define a compatible string for the Mali Valhall GPU
for MediaTek's SoC platform.
Signed-off-by: Nick Fan <Nick.Fan@...iatek.com>
---
.../bindings/gpu/arm,mali-valhall.yaml | 201 ++++++++++++++++++
1 file changed, 201 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
new file mode 100644
index 000000000000..526384d1e3ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall.yaml
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpu/arm,mali-valhall.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Mali Valhall GPU
+
+maintainers:
+ - Rob Herring <robh@...nel.org>
+
+properties:
+ $nodename:
+ pattern: '^gpu@[a-f0-9]+$'
+
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8192-mali
+ - const: arm,mali-valhall
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Job interrupt
+ - description: MMU interrupt
+ - description: GPU interrupt
+
+ interrupt-names:
+ items:
+ - const: job
+ - const: mmu
+ - const: gpu
+
+ clocks:
+ minItems: 1
+
+ power-domains:
+ minItems: 1
+ maxItems: 5
+
+ mali-supply: true
+ sram-supply: true
+
+ operating-points-v2: true
+ opp-table: true
+
+ "#cooling-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8192-mali
+ then:
+ properties:
+ power-domains:
+ minItems: 5
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: core0
+ - const: core1
+ - const: core2
+ - const: core3
+ - const: core4
+
+ required:
+ - sram-supply
+ - power-domains
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gpu@...00000 {
+ compatible = "mediatek,mt8192-mali", "arm,mali-valhall";
+ reg = <0x13000000 0x4000>;
+ interrupts =
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names =
+ "gpu",
+ "mmu",
+ "job";
+
+ clocks = <&mfgcfg 0>;
+
+ power-domains =
+ <&spm 4>,
+ <&spm 5>,
+ <&spm 6>,
+ <&spm 7>,
+ <&spm 8>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+ mali-supply = <&mt6315_7_vbuck1>;
+ sram-supply = <&mt6359_vsram_others_ldo_reg>;
+ gpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ opp-microvolt = <606250>, <750000>;
+ };
+
+ opp-399000000 {
+ opp-hz = /bits/ 64 <399000000>;
+ opp-microvolt = <618750>, <750000>;
+ };
+
+ opp-440000000 {
+ opp-hz = /bits/ 64 <440000000>;
+ opp-microvolt = <631250>, <750000>;
+ };
+
+ opp-482000000 {
+ opp-hz = /bits/ 64 <482000000>;
+ opp-microvolt = <643750>, <750000>;
+ };
+
+ opp-523000000 {
+ opp-hz = /bits/ 64 <523000000>;
+ opp-microvolt = <656250>, <750000>;
+ };
+
+ opp-564000000 {
+ opp-hz = /bits/ 64 <564000000>;
+ opp-microvolt = <668750>, <750000>;
+ };
+
+ opp-605000000 {
+ opp-hz = /bits/ 64 <605000000>;
+ opp-microvolt = <681250>, <750000>;
+ };
+
+ opp-647000000 {
+ opp-hz = /bits/ 64 <647000000>;
+ opp-microvolt = <693750>, <750000>;
+ };
+
+ opp-688000000 {
+ opp-hz = /bits/ 64 <688000000>;
+ opp-microvolt = <706250>, <750000>;
+ };
+
+ opp-724000000 {
+ opp-hz = /bits/ 64 <724000000>;
+ opp-microvolt = <725000>, <750000>;
+ };
+
+ opp-748000000 {
+ opp-hz = /bits/ 64 <748000000>;
+ opp-microvolt = <737500>, <750000>;
+ };
+
+ opp-772000000 {
+ opp-hz = /bits/ 64 <772000000>;
+ opp-microvolt = <750000>, <750000>;
+ };
+
+ opp-795000000 {
+ opp-hz = /bits/ 64 <795000000>;
+ opp-microvolt = <762500>, <762500>;
+ };
+
+ opp-819000000 {
+ opp-hz = /bits/ 64 <819000000>;
+ opp-microvolt = <775000>, <775000>;
+ };
+
+ opp-843000000 {
+ opp-hz = /bits/ 64 <843000000>;
+ opp-microvolt = <787500>, <787500>;
+ };
+
+ opp-866000000 {
+ opp-hz = /bits/ 64 <866000000>;
+ opp-microvolt = <800000>, <800000>;
+ };
+ };
+ };
+...
--
2.18.0
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