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Message-ID: <20220415125221.2871991-5-conor.dooley@microchip.com>
Date:   Fri, 15 Apr 2022 13:52:22 +0100
From:   Conor Dooley <conor.dooley@...rochip.com>
To:     Palmer Dabbelt <palmer@...belt.com>
CC:     Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        <linux-kernel@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
        Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v1 4/4] MAINTAINERS: add polarfire rng, pci and clock drivers

Hardware random, PCI and clock drivers for the PolarFire SoC have been
upstreamed but are not covered by the MAINTAINERS entry, so add them.

Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
 MAINTAINERS | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index fd768d43e048..a1df9c89bd11 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16944,7 +16944,10 @@ M:	Conor Dooley <conor.dooley@...rochip.com>
 L:	linux-riscv@...ts.infradead.org
 S:	Supported
 F:	arch/riscv/boot/dts/microchip/
+F:	drivers/char/hw_random/mpfs-rng.c
+F:	drivers/clk/microchip/clk-mpfs.c
 F:	drivers/mailbox/mailbox-mpfs.c
+F:	drivers/pci/controller/pcie-microchip-host.c
 F:	drivers/soc/microchip/
 F:	include/soc/microchip/mpfs.h
 
-- 
2.35.2

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