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Message-Id: <20220415165939.1861470-2-fparent@baylibre.com>
Date: Fri, 15 Apr 2022 18:59:39 +0200
From: Fabien Parent <fparent@...libre.com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>
Cc: Fabien Parent <fparent@...libre.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH 2/2] arm64: dts: mediatek: mt8195: add UFS HCI node
Add the node for the UFS HCI controller for the MediaTek MT8195 SoC.
Signed-off-by: Fabien Parent <fparent@...libre.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index b57e620c2c72..2255e19cc3b2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -619,6 +619,30 @@ mmc2: mmc@...50000 {
status = "disabled";
};
+ ufshci: ufshci@...70000 {
+ compatible = "mediatek,mt8195-ufshci",
+ "mediatek,mt8183-ufshci";
+ reg = <0 0x11270000 0 0x2300>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&ufsphy>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>,
+ <&infracfg_ao CLK_INFRA_AO_AES>,
+ <&infracfg_ao CLK_INFRA_AO_UFS_TICK>,
+ <&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>,
+ <&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>,
+ <&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>,
+ <&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>,
+ <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>;
+ clock-names = "ufs", "ufs_aes", "ufs_tick",
+ "unipro_sysclk", "unipro_tick",
+ "unipro_mp_bclk", "ufs_tx_symbol",
+ "ufs_mem_sub";
+ freq-table-hz = <0 0>, <0 0>, <0 0>,
+ <0 0>, <0 0>, <0 0>,
+ <0 0>, <0 0>;
+ status = "disabled";
+ };
+
xhci1: usb@...90000 {
compatible = "mediatek,mt8195-xhci",
"mediatek,mtk-xhci";
--
2.35.2
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