lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 18 Apr 2022 15:57:18 +0800
From:   Shawn Guo <shawnguo@...nel.org>
To:     Tim Harvey <tharvey@...eworks.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Device Tree Mailing List <devicetree@...r.kernel.org>,
        Linux ARM Mailing List <linux-arm-kernel@...ts.infradead.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] imx8mm-venice-gw7902: update pci refclk

On Mon, Apr 11, 2022 at 12:44:23PM -0700, Tim Harvey wrote:
> On Sun, Apr 10, 2022 at 6:31 PM Shawn Guo <shawnguo@...nel.org> wrote:
> >
> > On Tue, Apr 05, 2022 at 01:06:25PM -0700, Tim Harvey wrote:
> > > Use the correct PCI clock bindings.
> >
> > Please improve the commit log to explain why clock "pcie_phy" can be
> > dropped.
> >
> 
> Shawn,
> 
> The original PCIe bindings for this board were wrong - they were from
> a version of the bindings that was not yet approved (my mistake) and
> I'm just trying to bring them up to date.
> 
> That said, I looked at the latest fsl,imx6q-pcie.yaml dt-bindings [1]
> and see that there should be a min of 3 clocks called 'pcie',
> 'pcie_bus', and 'pcie_phy'. However I notice that all of the current
> imx8mm boards that enable PCI have clock-names of 'pcie', 'pcie_aux',
> and 'pcie_bus'. It seems like all the imx8mm boards having pcie have
> clock-names this way:
> 
> arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> 
> Does the binding need to change or do the clock names need to change
> in the above?

If the bindings is approved/correct, device tree should match bindings.

Shawn

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ