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Message-ID: <Yl0/v2101wx6hy7B@matsya>
Date: Mon, 18 Apr 2022 16:08:55 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Frank Wunderlich <linux@...web.de>
Cc: linux-rockchip@...ts.infradead.org,
Frank Wunderlich <frank-w@...lic-files.de>,
Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Krzysztof Wilczyński <kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Johan Jonker <jbx6244@...il.com>,
Peter Geis <pgwipeout@...il.com>,
Michael Riesch <michael.riesch@...fvision.net>,
linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org
Subject: Re: [RFC/RFT 3/6] phy: rockchip: Support pcie v3
On 16-04-22, 15:54, Frank Wunderlich wrote:
> From: Frank Wunderlich <frank-w@...lic-files.de>
>
> RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566.
> It use a dedicated pcie-phy. Add support for this.
>
> Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
> ---
> driver was taken from linux 5.10 based on in
> https://github.com/JeffyCN/mirrors
> which now has disappeared
> ---
> drivers/phy/rockchip/Kconfig | 9 +
> drivers/phy/rockchip/Makefile | 1 +
> .../phy/rockchip/phy-rockchip-snps-pcie3.c | 278 ++++++++++++++++++
> include/dt-bindings/phy/phy-snps-pcie3.h | 21 ++
> include/linux/phy/pcie.h | 12 +
> 5 files changed, 321 insertions(+)
> create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
> create mode 100644 include/dt-bindings/phy/phy-snps-pcie3.h
> create mode 100644 include/linux/phy/pcie.h
>
> diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
> index 9022e395c056..94360fc96a6f 100644
> --- a/drivers/phy/rockchip/Kconfig
> +++ b/drivers/phy/rockchip/Kconfig
> @@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE
> help
> Enable this to support the Rockchip PCIe PHY.
>
> +config PHY_ROCKCHIP_SNPS_PCIE3
> + tristate "Rockchip Snps PCIe3 PHY Driver"
> + depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
> + depends on HAS_IOMEM
> + select GENERIC_PHY
> + select MFD_SYSCON
> + help
> + Enable this to support the Rockchip snps PCIe3 PHY.
> +
> config PHY_ROCKCHIP_TYPEC
> tristate "Rockchip TYPEC PHY Driver"
> depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST)
> diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
> index a5041efb5b8f..7eab129230d1 100644
> --- a/drivers/phy/rockchip/Makefile
> +++ b/drivers/phy/rockchip/Makefile
> @@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
> obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
> obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
> obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
> +obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
> obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
> new file mode 100644
> index 000000000000..992b9709a97a
> --- /dev/null
> +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
> @@ -0,0 +1,278 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip PCIE3.0 phy driver
> + *
> + * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/pcie.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <dt-bindings/phy/phy-snps-pcie3.h>
> +
> +/* Register for RK3568 */
> +#define GRF_PCIE30PHY_CON1 0x4
> +#define GRF_PCIE30PHY_CON6 0x18
> +#define GRF_PCIE30PHY_CON9 0x24
> +#define GRF_PCIE30PHY_STATUS0 0x80
> +#define SRAM_INIT_DONE(reg) (reg & BIT(14))
> +
> +/* Register for RK3588 */
> +#define PHP_GRF_PCIESEL_CON 0x100
> +#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
> +#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
> +#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
> +#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
> +
> +struct rockchip_p3phy_ops;
> +
> +struct rockchip_p3phy_priv {
> + const struct rockchip_p3phy_ops *ops;
> + void __iomem *mmio;
> + /* mode: RC, EP */
> + int mode;
> + /* pcie30_phymode: Aggregation, Bifurcation */
> + int pcie30_phymode;
> + struct regmap *phy_grf;
> + struct regmap *pipe_grf;
> + struct reset_control *p30phy;
> + struct phy *phy;
> + struct clk_bulk_data *clks;
> + int num_clks;
> + bool is_bifurcation;
> +};
> +
> +struct rockchip_p3phy_ops {
> + int (*phy_init)(struct rockchip_p3phy_priv *priv);
> +};
> +
> +static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> + struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
> +
> + /* Actually We don't care EP/RC mode, but just record it */
> + switch (submode) {
> + case PHY_MODE_PCIE_RC:
> + priv->mode = PHY_MODE_PCIE_RC;
> + break;
> + case PHY_MODE_PCIE_EP:
> + priv->mode = PHY_MODE_PCIE_EP;
> + break;
> + case PHY_MODE_PCIE_BIFURCATION:
> + priv->is_bifurcation = true;
> + break;
> + default:
> + pr_info("%s, invalid mode\n", __func__);
this should be err log, also make it dev_err pls
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
> +{
> + int ret = 0;
initialization seems superfluous
> + u32 reg;
> +
> + /* Deassert PCIe PMA output clamp mode */
> + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
> + (0x1 << 15) | (0x1 << 31));
magic numbers.. sounds like BIT(15) and BIT(31)
> + /* Set bifurcation if needed, and it doesn't care RC/EP */
> + if (priv->is_bifurcation) {
> + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
> + 0x1 | (0xf << 16));
> + regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
> + (0x1 << 15) | (0x1 << 31));
> + }
> +
> + reset_control_deassert(priv->p30phy);
> +
> + ret = regmap_read_poll_timeout(priv->phy_grf,
> + GRF_PCIE30PHY_STATUS0,
> + reg, SRAM_INIT_DONE(reg),
> + 0, 500);
> + if (ret)
> + pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
> + __func__, reg);
dev_err() pls
> + return ret;
> +}
> +
> +static const struct rockchip_p3phy_ops rk3568_ops = {
> + .phy_init = rockchip_p3phy_rk3568_init,
> +};
> +
> +static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
> +{
> + int ret = 0;
superfluous init again
--
~Vinod
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