linux-kernel - Re: [PATCH 1/7] clk: mediatek: reset: Correct the logic of setting register

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Message-ID: <7e6ca7055ad6c236cb43b73c0b32a435033bb37d.camel@mediatek.com>
Date:   Tue, 19 Apr 2022 14:38:40 +0800
From:   Rex-BC Chen <rex-bc.chen@...iatek.com>
To:     Chen-Yu Tsai <wenst@...omium.org>
CC:     <mturquette@...libre.com>, <sboyd@...nel.org>,
        <matthias.bgg@...il.com>, <p.zabel@...gutronix.de>,
        <angelogioacchino.delregno@...labora.com>,
        <chun-jie.chen@...iatek.com>, <yong.liang@...iatek.com>,
        <runyang.chen@...iatek.com>, <linux-kernel@...r.kernel.org>,
        <allen-kh.cheng@...iatek.com>, <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH 1/7] clk: mediatek: reset: Correct the logic of setting
 register

On Tue, 2022-04-19 at 13:48 +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Mon, Apr 18, 2022 at 9:22 PM Rex-BC Chen <rex-bc.chen@...iatek.com
> > wrote:
> > 
> 
> The subject could be written as "Fix written reset bit offset" to
> make it
> more specific.

Hello ChenYu,

I will update the topic in next version.
Thanks for your suggestion.

BRs,
Rex

> 
> > Original assert/deassert bit is BIT(0), but it's more resonable to
> > modify
> > them to BIT(id % 32) which is based on id.
> > 
> > This patch will not influence any previous driver because the reset
> > is
> > only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is
> > 0.
> > 
> > Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
> 
> Otherwise,
> 
> Reviewed-by: Chen-Yu Tsai <wenst@...omium.org>