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Message-ID: <CAJ9a7ViDkaqykQTiPX7T7z0T0cDOfnyDM6H7sY=dNDe0DqZwDw@mail.gmail.com>
Date:   Tue, 19 Apr 2022 10:23:23 +0100
From:   Mike Leach <mike.leach@...aro.org>
To:     Mao Jinlong <quic_jinlmao@...cinc.com>
Cc:     Mathieu Poirier <mathieu.poirier@...aro.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Leo Yan <leo.yan@...aro.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Tingwei Zhang <quic_tingweiz@...cinc.com>,
        Yuanfang Zhang <quic_yuanfang@...cinc.com>,
        Tao Zhang <quic_taozha@...cinc.com>,
        Trilok Soni <quic_tsoni@...cinc.com>,
        Hao Zhang <quic_hazha@...cinc.com>,
        linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support

Hi,

On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@...cinc.com> wrote:
>
> TPDM serves as data collection component for various dataset types.
> DSB(Discrete Single Bit) is one of the dataset types. DSB subunit
> can be enabled for data collection by writing 1 to the first bit of
> DSB_CR register. This change is to add enable/disable function for
> DSB dataset by writing DSB_CR register.
>
> Signed-off-by: Tao Zhang <quic_taozha@...cinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@...cinc.com>
> ---
>  drivers/hwtracing/coresight/coresight-tpdm.c | 61 ++++++++++++++++++++
>  drivers/hwtracing/coresight/coresight-tpdm.h | 21 +++++++
>  2 files changed, 82 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> index 3900ae50670a..d7b970cdcf51 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -20,7 +20,28 @@
>
>  DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
>
> +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
> +{
> +       u32 val;
> +
> +       /* Set the enable bit of DSB control register to 1 */
> +       val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
> +       val = val | BIT(0);

Please use #defined values, declared in the header file rather than
BIT(x) here. (the etm4x drivers have been recently updated to use the
same pattern).
e.g.
 val |= TPDM_DSB_CR_ENA;

> +       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
> +}
> +
>  /* TPDM enable operations */
> +static void _tpdm_enable(struct tpdm_drvdata *drvdata)
> +{
> +       CS_UNLOCK(drvdata->base);
> +
> +       /* Check if DSB datasets is present for TPDM. */
> +       if (test_bit(TPDM_DS_DSB, drvdata->datasets))
> +               tpdm_enable_dsb(drvdata);
> +
> +       CS_LOCK(drvdata->base);
> +}
> +
>  static int tpdm_enable(struct coresight_device *csdev,
>                        struct perf_event *event, u32 mode)
>  {
> @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev,
>                 return -EBUSY;
>         }
>
> +       _tpdm_enable(drvdata);
>         drvdata->enable = true;
>         mutex_unlock(&drvdata->lock);
>
> @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev,
>         return 0;
>  }
>
> +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
> +{
> +       u32 val;
> +
> +       /* Set the enable bit of DSB control register to 0 */
> +       val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
> +       val = val & ~BIT(0);

val &= ~TPDM_DSB_CR_ENA;

> +       writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
> +}
> +
>  /* TPDM disable operations */
> +static void _tpdm_disable(struct tpdm_drvdata *drvdata)
> +{
> +       CS_UNLOCK(drvdata->base);
> +
> +       /* Check if DSB datasets is present for TPDM. */
> +       if (test_bit(TPDM_DS_DSB, drvdata->datasets))
> +               tpdm_disable_dsb(drvdata);
> +
> +       CS_LOCK(drvdata->base);
> +
> +}
> +
>  static void tpdm_disable(struct coresight_device *csdev,
>                          struct perf_event *event)
>  {
> @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev,
>                 return;
>         }
>
> +       _tpdm_disable(drvdata);
>         drvdata->enable = false;
>         mutex_unlock(&drvdata->lock);
>
> @@ -66,6 +111,21 @@ static const struct coresight_ops tpdm_cs_ops = {
>         .source_ops     = &tpdm_source_ops,
>  };
>
> +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
> +{
> +       int i;
> +       u32 pidr;
> +
> +       CS_UNLOCK(drvdata->base);
> +       /*  Get the datasets present on the TPDM. */
> +       pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
> +       for (i = 0; i < TPDM_DATASETS; i++) {
> +               if (pidr & BIT(i))
> +                       __set_bit(i, drvdata->datasets);

Could this be considerably simpified? - there are a maximum of 7 bits
for datasets - and you are setting the same bit in drvdata->datasets
for each bit in pidr

e.g. if the datasets declaration is a simple unsigned long, then the
following is easier to read and understand:

drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0);

The tests above could then become:
if (drvdata->datasets & BIT(TPDM_DS_DSB)) ...


> +       }
> +       CS_LOCK(drvdata->base);
> +}
> +
>  static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
>  {
>         struct device *dev = &adev->dev;
> @@ -104,6 +164,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
>         if (IS_ERR(drvdata->csdev))
>                 return PTR_ERR(drvdata->csdev);
>
> +       tpdm_init_default_data(drvdata);
>         /* Decrease pm refcount when probe is done.*/
>         pm_runtime_put(&adev->dev);
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
> index 94a7748a5426..8f05070879c4 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.h
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
> @@ -6,6 +6,25 @@
>  #ifndef _CORESIGHT_CORESIGHT_TPDM_H
>  #define _CORESIGHT_CORESIGHT_TPDM_H
>
> +/* The max number of the datasets that TPDM supports */
> +#define TPDM_DATASETS       7
> +
> +/* DSB Subunit Registers */
> +#define TPDM_DSB_CR            (0x780)
> +

declare the enable bit here with comment documenting usage  - see above.

> +/**
> + * This enum is for PERIPHIDR0 register of TPDM.
> + * The fields [6:0] of PERIPHIDR0 are used to determine what
> + * interfaces and subunits are present on a given TPDM.
> + *
> + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
> + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
> + */
> +enum tpdm_dataset {
> +       TPDM_DS_IMPLDEF,
> +       TPDM_DS_DSB,
> +};
> +
>  /**
>   * struct tpdm_drvdata - specifics associated to an TPDM component
>   * @base:       memory mapped base address for this component.
> @@ -13,6 +32,7 @@
>   * @csdev:      component vitals needed by the framework.
>   * @lock:       lock for the enable value.
>   * @enable:     enable status of the component.
> + * @datasets:   The datasets types present of the TPDM.
>   */
>
>  struct tpdm_drvdata {
> @@ -21,6 +41,7 @@ struct tpdm_drvdata {
>         struct coresight_device *csdev;
>         struct mutex            lock;
>         bool                    enable;
> +       DECLARE_BITMAP(datasets, TPDM_DATASETS);

Could this simply be declared as an unsigned long? - then simplify the
code in the .c file.

Regards

Mike

>  };
>
>  #endif  /* _CORESIGHT_CORESIGHT_TPDM_H */
> --
> 2.17.1
>


-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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