linux-kernel - Re: [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 19 Apr 2022 14:45:30 +0300
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Ben Chuang <benchuanggli@...il.com>, ulf.hansson@...aro.org
Cc:     SeanHY.Chen@...esyslogic.com.tw, ben.chuang@...esyslogic.com.tw,
        greg.tu@...esyslogic.com.tw, linux-kernel@...r.kernel.org,
        linux-mmc@...r.kernel.org
Subject: Re: [RESEND, PATCH] mmc: sdhci-pci-gli: A workaround to allow GL9755
 to enter ASPM L1.2

On 14/04/22 12:49, Ben Chuang wrote:
> From: Ben Chuang <ben.chuang@...esyslogic.com.tw>
> 
> When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
> enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter
> ASPM L1.2.
> 
> Signed-off-by: Ben Chuang <ben.chuang@...esyslogic.com.tw>

Acked-by: Adrian Hunter <adrian.hunter@...el.com>

> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 97035d77c18c..52230857388f 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -137,6 +137,9 @@
>  #define PCI_GLI_9755_SerDes  0x70
>  #define PCI_GLI_9755_SCP_DIS   BIT(19)
>  
> +#define PCI_GLI_9755_PM_CTRL     0xFC
> +#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
> +
>  #define GLI_MAX_TUNING_LOOP 40
>  
>  /* Genesys Logic chipset */
> @@ -597,6 +600,13 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
>  			    GLI_9755_CFG2_L1DLY_VALUE);
>  	pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
>  
> +	/* toggle PM state to allow GL9755 to enter ASPM L1.2 */
> +	pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
> +	value |= PCI_GLI_9755_PM_STATE;
> +	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +	value &= ~PCI_GLI_9755_PM_STATE;
> +	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +
>  	gl9755_wt_off(pdev);
>  }
>