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Message-Id: <20220420191926.3411830-1-michael@walle.cc>
Date: Wed, 20 Apr 2022 21:19:24 +0200
From: Michael Walle <michael@...le.cc>
To: Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Lars Povlsen <lars.povlsen@...rochip.com>
Cc: linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Horatiu Vultur <horatiu.vultur@...rochip.com>,
Michael Walle <michael@...le.cc>
Subject: [PATCH v3 0/2] pinctrl: ocelot: add shared reset
On LAN966x SoCs, there is an internal reset which is used to reset the
switch core. But this will also reset the GPIO and the SGPIO. Thus add
support for this shared reset line.
changes since v2:
- use dev_err_probe(), thanks Horatiu
changes since v1:
- rebased onto linus' devel tree, former patch was still based on
v1 of the YAML conversion patch
Michael Walle (2):
dt-bindings: pinctrl: ocelot: add reset property
pinctrl: ocelot: add optional shared reset
.../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 8 ++++++++
drivers/pinctrl/pinctrl-ocelot.c | 8 ++++++++
2 files changed, 16 insertions(+)
--
2.30.2
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