linux-kernel - Re: [PATCH 3/5] dt-bindings: mediatek: add vdosys1 RDMA definition for mt8195

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Message-ID: <0b85798f63deb0c943ed1803aaa06cde6437e7bd.camel@mediatek.com>
Date:   Wed, 20 Apr 2022 11:15:30 +0800
From:   Rex-BC Chen <rex-bc.chen@...iatek.com>
To:     Chun-Kuang Hu <chunkuang.hu@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>
CC:     Rob Herring <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        David Airlie <airlied@...ux.ie>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        Jason-JH Lin (林睿祥) 
        <Jason-JH.Lin@...iatek.com>,
        Nancy Lin (林欣螢) 
        <Nancy.Lin@...iatek.com>, DTML <devicetree@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        DRI Development <dri-devel@...ts.freedesktop.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH 3/5] dt-bindings: mediatek: add vdosys1 RDMA definition
 for mt8195

On Tue, 2022-04-19 at 23:51 +0800, Chun-Kuang Hu wrote:
> Matthias Brugger <matthias.bgg@...il.com> 於 2022年4月19日 週二 下午10:57寫道：
> > 
> > 
> > 
> > On 19/04/2022 05:32, Rex-BC Chen wrote:
> > > From: "Nancy.Lin" <nancy.lin@...iatek.com>
> > > 
> > > Add vdosys1 RDMA definition.
> > > 
> > > Signed-off-by: Nancy.Lin <nancy.lin@...iatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@...labora.com>
> > > ---
> > >   .../display/mediatek/mediatek,mdp-rdma.yaml   | 86
> > > +++++++++++++++++++
> > >   1 file changed, 86 insertions(+)
> > >   create mode 100644
> > > Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-
> > > rdma.yaml
> > > 
> > > diff --git
> > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp
> > > -rdma.yaml
> > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp
> > > -rdma.yaml
> > > new file mode 100644
> > > index 000000000000..6ab773569462
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp
> > > -rdma.yaml
> > > @@ -0,0 +1,86 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: 
> > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mdp-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!2Ig4llRcam253qgvT99ty3TWC4Yo6D6Dy1DgFiNuA_fMhtu1lJHERS1f4pzOBELsqIl__FAiHl5bJCAJqNc7FAWGTw$
> > >  
> > > +$schema: 
> > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!2Ig4llRcam253qgvT99ty3TWC4Yo6D6Dy1DgFiNuA_fMhtu1lJHERS1f4pzOBELsqIl__FAiHl5bJCAJqNdU9sgsvg$
> > >  
> > > +
> > > +title: MediaTek MDP RDMA
> > > +
> > > +maintainers:
> > > +  - Matthias Brugger <matthias.bgg@...il.com>
> > 
> > I don't think I would be the correct person to maintain this. This
> > should be the
> > person that is maintaining the driver.
> 
> Agree. This should be
> 
> Chun-Kuang Hu <chunkuang.hu@...nel.org>
> Philipp Zabel <p.zabel@...gutronix.de>
> 
> Regards,
> Chun-Kuang.
> 
> > 
> > Regards,
> > Matthias
> > 

Hello Chun-Kuang and Matthias,

OK, I will update the list in next version.

BRs,
Rex

> > > +
> > > +description: |
> > > +  The mediatek MDP RDMA stands for Read Direct Memory Access.
> > > +  It provides real time data to the back-end panel driver, such
> > > as DSI,
> > > +  DPI and DP_INTF.
> > > +  It contains one line buffer to store the sufficient pixel
> > > data.
> > > +  RDMA device node must be siblings to the central MMSYS_CONFIG
> > > node.
> > > +  For a description of the MMSYS_CONFIG binding, see
> > > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.
> > > yaml for details.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    oneOf:
> > > +      - items:
> > > +          - const: mediatek,mt8195-vdo1-rdma
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  interrupts:
> > > +    maxItems: 1
> > > +
> > > +  power-domains:
> > > +    description: A phandle and PM domain specifier as defined by
> > > bindings of
> > > +      the power controller specified by phandle. See
> > > +      Documentation/devicetree/bindings/power/power-domain.yaml
> > > for details.
> > > +
> > > +  clocks:
> > > +    items:
> > > +      - description: RDMA Clock
> > > +
> > > +  iommus:
> > > +    description:
> > > +      This property should point to the respective IOMMU block
> > > with master port as argument,
> > > +      see
> > > Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
> > > details.
> > > +
> > > +  mediatek,gce-client-reg:
> > > +    description:
> > > +      The register of display function block to be set by gce.
> > > There are 4 arguments,
> > > +      such as gce node, subsys id, offset and register size. The
> > > subsys id that is
> > > +      mapping to the register of display function blocks is
> > > defined in the gce header
> > > +      include/include/dt-bindings/gce/<chip>-gce.h of each
> > > chips.
> > > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > > +    maxItems: 1
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - power-domains
> > > +  - clocks
> > > +  - iommus
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +    #include <dt-bindings/clock/mt8195-clk.h>
> > > +    #include <dt-bindings/power/mt8195-power.h>
> > > +    #include <dt-bindings/gce/mt8195-gce.h>
> > > +    #include <dt-bindings/memory/mt8195-memory-port.h>
> > > +
> > > +    soc {
> > > +        #address-cells = <2>;
> > > +        #size-cells = <2>;
> > > +
> > > +        vdo1_rdma0: mdp-rdma@...04000 {
> > > +            compatible = "mediatek,mt8195-vdo1-rdma";
> > > +            reg = <0 0x1c104000 0 0x1000>;
> > > +            interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> > > +            clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> > > +            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> > > +            iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> > > +            mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX
> > > 0x4000 0x1000>;
> > > +        };
> > > +    };