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Message-ID: <20220420073440.31649-1-irui.wang@mediatek.com>
Date: Wed, 20 Apr 2022 15:34:39 +0800
From: Irui Wang <irui.wang@...iatek.com>
To: Hans Verkuil <hverkuil-cisco@...all.nl>,
Rob Herring <robh+dt@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Yunfei Dong <yunfei.dong@...iatek.com>
CC: Maoguang Meng <maoguang.meng@...iatek.com>,
Longfei Wang <longfei.wang@...iatek.com>,
Irui Wang <irui.wang@...iatek.com>,
<allen-kh.cheng@...iatek.com>, <linux-media@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<srv_heupstream@...iatek.com>,
<linux-mediatek@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH] dt-bindings: media: mtk-vcodec: Adds encoder power domain property
Adds encoder power domain property
Signed-off-by: Irui Wang <irui.wang@...iatek.com>
---
.../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
index deb5b657a2d5..3c069c965992 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
@@ -41,6 +41,9 @@ properties:
assigned-clock-parents: true
+ power-domains:
+ maxItems: 1
+
iommus:
minItems: 1
maxItems: 32
@@ -72,6 +75,7 @@ required:
- iommus
- assigned-clocks
- assigned-clock-parents
+ - power-domains
allOf:
- if:
@@ -132,6 +136,7 @@ examples:
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/memory/mt8173-larb-port.h>
#include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/mt8173-power.h>
vcodec_enc_avc: vcodec@...02000 {
compatible = "mediatek,mt8173-vcodec-enc";
@@ -153,6 +158,7 @@ examples:
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
};
vcodec_enc_vp8: vcodec@...02000 {
@@ -173,4 +179,5 @@ examples:
clock-names = "venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
};
--
2.18.0
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