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Message-ID: <CAH=2NtweJYnbtNwt93u+5VfWnLD7AfBob-LmBrE+g_U68qtfbw@mail.gmail.com>
Date:   Wed, 20 Apr 2022 13:14:21 +0530
From:   Bhupesh Sharma <bhupesh.sharma@...aro.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     linux-arm-msm@...r.kernel.org, bhupesh.linux@...il.com,
        agross@...nel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, robh+dt@...nel.org,
        Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: sm8150: Add support for SDC2

Hi Bjorn,

On Wed, 20 Apr 2022 at 08:26, Bjorn Andersson
<bjorn.andersson@...aro.org> wrote:
>
> On Thu 14 Apr 16:31 CDT 2022, Bhupesh Sharma wrote:
>
> > Add support for SDC2 which can be used to interface uSD card.
> >
> > Cc: Bjorn Andersson <bjorn.andersson@...aro.org>
> > Cc: Rob Herring <robh@...nel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@...aro.org>
>
> Thanks for the patch Bhupesh. I have already applied v1 though. Can you
> please double check linux-next to confirm that things are in order?

Sure, I will send a minor iommu sid related fix shortly as a separate
patch, which
is required to fix a ADMA error while using the microSD card on the ADP board
(after rebasing it to linux-next/master tip).

Regards,
Bhupesh

> > ---
> >  arch/arm64/boot/dts/qcom/sm8150.dtsi | 45 ++++++++++++++++++++++++++++
> >  1 file changed, 45 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > index 15f3bf2e7ea0..0fecebf0a473 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > @@ -3270,6 +3270,51 @@ usb_2_ssphy: phy@...b200 {
> >                       };
> >               };
> >
> > +             sdhc_2: sdhci@...4000 {
> > +                     compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5";
> > +                     reg = <0 0x08804000 0 0x1000>;
> > +
> > +                     interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > +                     interrupt-names = "hc_irq", "pwr_irq";
> > +
> > +                     clocks = <&gcc GCC_SDCC2_AHB_CLK>,
> > +                              <&gcc GCC_SDCC2_APPS_CLK>,
> > +                              <&rpmhcc RPMH_CXO_CLK>;
> > +                     clock-names = "iface", "core", "xo";
> > +                     iommus = <&apps_smmu 0x6a0 0x0>;
> > +                     qcom,dll-config = <0x0007642c>;
> > +                     qcom,ddr-config = <0x80040868>;
> > +                     power-domains = <&rpmhpd 0>;
> > +                     operating-points-v2 = <&sdhc2_opp_table>;
> > +
> > +                     status = "disabled";
> > +
> > +                     sdhc2_opp_table: sdhc2-opp-table {
> > +                             compatible = "operating-points-v2";
> > +
> > +                             opp-19200000 {
> > +                                     opp-hz = /bits/ 64 <19200000>;
> > +                                     required-opps = <&rpmhpd_opp_min_svs>;
> > +                             };
> > +
> > +                             opp-50000000 {
> > +                                     opp-hz = /bits/ 64 <50000000>;
> > +                                     required-opps = <&rpmhpd_opp_low_svs>;
> > +                             };
> > +
> > +                             opp-100000000 {
> > +                                     opp-hz = /bits/ 64 <100000000>;
> > +                                     required-opps = <&rpmhpd_opp_svs>;
> > +                             };
> > +
> > +                             opp-202000000 {
> > +                                     opp-hz = /bits/ 64 <202000000>;
> > +                                     required-opps = <&rpmhpd_opp_svs_l1>;
> > +                             };
> > +                     };
> > +             };
> > +
> >               dc_noc: interconnect@...0000 {
> >                       compatible = "qcom,sm8150-dc-noc";
> >                       reg = <0 0x09160000 0 0x3200>;
> > --
> > 2.35.1
> >

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