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Date:   Wed, 20 Apr 2022 21:05:22 +0800
From:   Rex-BC Chen <rex-bc.chen@...iatek.com>
To:     <mturquette@...libre.com>, <sboyd@...nel.org>
CC:     <matthias.bgg@...il.com>, <p.zabel@...gutronix.de>,
        <angelogioacchino.delregno@...labora.com>,
        <chun-jie.chen@...iatek.com>, <wenst@...omium.org>,
        <runyang.chen@...iatek.com>, <linux-kernel@...r.kernel.org>,
        <allen-kh.cheng@...iatek.com>, <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Rex-BC Chen <rex-bc.chen@...iatek.com>
Subject: [PATCH V2 07/12] clk: mediatek: reset: Add return for clock reset register function

To make error handling, we add return for mtk_clk_register_rst_ctrl().

Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
---
 drivers/clk/mediatek/reset.c | 14 ++++++++------
 drivers/clk/mediatek/reset.h |  4 ++--
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index d67c13958458..b164b1da7dd3 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -64,8 +64,8 @@ static const struct reset_control_ops *rst_op[MTK_RST_MAX] = {
 	[MTK_RST_SET_CLR] = &mtk_reset_ops_set_clr,
 };
 
-void mtk_clk_register_rst_ctrl(struct device_node *np,
-			       const struct mtk_clk_rst_desc *desc)
+int mtk_clk_register_rst_ctrl(struct device_node *np,
+			      const struct mtk_clk_rst_desc *desc)
 {
 	struct regmap *regmap;
 	struct mtk_clk_rst_data *data;
@@ -73,23 +73,23 @@ void mtk_clk_register_rst_ctrl(struct device_node *np,
 
 	if (!desc) {
 		pr_err("mtk clock reset desc is NULL\n");
-		return;
+		return -EINVAL;
 	}
 
 	if (desc->version >= MTK_RST_MAX) {
 		pr_err("Error version number: %d\n", desc->version);
-		return;
+		return -EINVAL;
 	}
 
 	regmap = device_node_to_regmap(np);
 	if (IS_ERR(regmap)) {
 		pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
-		return;
+		return -EINVAL;
 	}
 
 	data = kzalloc(sizeof(*data), GFP_KERNEL);
 	if (!data)
-		return;
+		return -ENOMEM;
 
 	data->desc = desc;
 	data->regmap = regmap;
@@ -103,6 +103,8 @@ void mtk_clk_register_rst_ctrl(struct device_node *np,
 		pr_err("could not register reset controller: %d\n", ret);
 		kfree(data);
 	}
+
+	return ret;
 }
 
 MODULE_LICENSE("GPL");
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 3a93f61e106e..d59f4b89384d 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -27,7 +27,7 @@ struct mtk_clk_rst_data {
 	const struct mtk_clk_rst_desc *desc;
 };
 
-void mtk_clk_register_rst_ctrl(struct device_node *np,
-			       const struct mtk_clk_rst_desc *desc);
+int mtk_clk_register_rst_ctrl(struct device_node *np,
+			      const struct mtk_clk_rst_desc *desc);
 
 #endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0

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