[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAK8P3a3MVZ=QGcU8DaZbc5eaAt_FvoEEnqLqTYa=+9w__VYEig@mail.gmail.com>
Date: Thu, 21 Apr 2022 09:36:46 +0200
From: Arnd Bergmann <arnd@...db.de>
To: Christoph Hellwig <hch@...radead.org>
Cc: Arnd Bergmann <arnd@...db.de>, Ard Biesheuvel <ardb@...nel.org>,
Catalin Marinas <catalin.marinas@....com>,
Herbert Xu <herbert@...dor.apana.org.au>,
Will Deacon <will@...nel.org>, Marc Zyngier <maz@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Andrew Morton <akpm@...ux-foundation.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Linux Memory Management List <linux-mm@...ck.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
"David S. Miller" <davem@...emloft.net>
Subject: Re: [PATCH 07/10] crypto: Use ARCH_DMA_MINALIGN instead of ARCH_KMALLOC_MINALIGN
On Thu, Apr 21, 2022 at 9:20 AM Christoph Hellwig <hch@...radead.org> wrote:
>
> Btw, there is another option: Most real systems already require having
> swiotlb to bounce buffer in some cases. We could simply force bounce
> buffering in the dma mapping code for too small or not properly aligned
> transfers and just decrease the dma alignment.
I like the idea because these days we already rely on bounce buffering
for sub-page buffers in many iommu based cases for strict isolation
purposes, as well as most 64-bit machines that lack an iommu.
Does this work on all 32-bit architectures as well? I see that you added
swiotlb for ARM LPASE systems in 2019, but I don't know if that has any
additional requirements for the other 32-bit architectures that don't
select SWIOTLB today.
Arnd
Powered by blists - more mailing lists