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Message-ID: <20220421035111.7267-4-allen-kh.cheng@mediatek.com>
Date: Thu, 21 Apr 2022 11:51:10 +0800
From: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
To: Mauro Carvalho Chehab <mchehab@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@...onical.com>
CC: <Project_Global_Chrome_Upstream_Group@...iatek.com>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>,
"Chen-Yu Tsai" <wenst@...omium.org>,
Ryder Lee <ryder.lee@...nel.org>,
Hui Liu <hui.liu@...iatek.com>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
"Irui Wang" <irui.wang@...iatek.com>
Subject: [PATCH 3/4] arm64: dts: mediatek: mt8173: Add power domain to encoder nodes
The power of encoder is not control by mediatek,larb, so we add
power domain to encoder nodes for mt8173 SoC.
Signed-off-by: Irui Wang <irui.wang@...iatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 10291b2690ab..eebc2d074254 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1470,6 +1470,7 @@
clock-names = "venc_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
};
jpegdec: jpegdec@...04000 {
@@ -1520,6 +1521,7 @@
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents =
<&topckgen CLK_TOP_VCODECPLL_370P5>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
};
};
};
--
2.18.0
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