| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20220422055659.8738-3-tinghan.shen@mediatek.com>
Date: Fri, 22 Apr 2022 13:56:57 +0800
From: Tinghan Shen <tinghan.shen@...iatek.com>
To: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
Liam Girdwood <lgirdwood@...il.com>,
Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
Daniel Baluta <daniel.baluta@....com>,
Mark Brown <broonie@...nel.org>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>,
Matthias Brugger <matthias.bgg@...il.com>,
YC Hung <yc.hung@...iatek.com>,
Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Tinghan Shen <tinghan.shen@...iatek.com>,
Péter Ujfalusi <peter.ujfalusi@...ux.intel.com>,
"Geert Uytterhoeven" <geert@...ux-m68k.org>
CC: <linux-kernel@...r.kernel.org>,
<sound-open-firmware@...a-project.org>,
<alsa-devel@...a-project.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH v1 2/4] ASoC: SOF: mediatek: Add mt8186 sof fw loader and dsp ops
Add mt8186-loader module with ops callback to load and run firmware
on mt8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@...iatek.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>
Reviewed-by: Yaochun Hung <yc.hung@...iatek.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
---
sound/soc/sof/mediatek/mt8186/Makefile | 2 +-
sound/soc/sof/mediatek/mt8186/mt8186-loader.c | 53 +++++++++++++++++++
sound/soc/sof/mediatek/mt8186/mt8186.c | 18 +++++++
sound/soc/sof/mediatek/mt8186/mt8186.h | 3 ++
4 files changed, 75 insertions(+), 1 deletion(-)
create mode 100644 sound/soc/sof/mediatek/mt8186/mt8186-loader.c
diff --git a/sound/soc/sof/mediatek/mt8186/Makefile b/sound/soc/sof/mediatek/mt8186/Makefile
index e0e971c17d5e..03a12f2096f9 100644
--- a/sound/soc/sof/mediatek/mt8186/Makefile
+++ b/sound/soc/sof/mediatek/mt8186/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
-snd-sof-mt8186-objs := mt8186.o
+snd-sof-mt8186-objs := mt8186.o mt8186-loader.o
obj-$(CONFIG_SND_SOC_SOF_MT8186) += snd-sof-mt8186.o
diff --git a/sound/soc/sof/mediatek/mt8186/mt8186-loader.c b/sound/soc/sof/mediatek/mt8186/mt8186-loader.c
new file mode 100644
index 000000000000..6ab4921b1010
--- /dev/null
+++ b/sound/soc/sof/mediatek/mt8186/mt8186-loader.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+//
+// Copyright (c) 2022 Mediatek Corporation. All rights reserved.
+//
+// Author: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
+// Tinghan Shen <tinghan.shen@...iatek.com>
+//
+// Hardware interface for mt8186 DSP code loader
+
+#include <sound/sof.h>
+#include "mt8186.h"
+#include "../../ops.h"
+
+void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
+{
+ /* set RUNSTALL to stop core */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
+ RUNSTALL, RUNSTALL);
+
+ /* set core boot address */
+ snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr);
+ snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0);
+
+ /* assert core reset */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
+ SW_RSTN_C0 | SW_DBG_RSTN_C0,
+ SW_RSTN_C0 | SW_DBG_RSTN_C0);
+
+ /* hardware requirement */
+ udelay(1);
+
+ /* release core reset */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
+ SW_RSTN_C0 | SW_DBG_RSTN_C0,
+ 0);
+
+ /* clear RUNSTALL (bit31) to start core */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
+ RUNSTALL, 0);
+}
+
+void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
+{
+ /* set RUNSTALL to stop core */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
+ RUNSTALL, RUNSTALL);
+
+ /* assert core reset */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
+ SW_RSTN_C0 | SW_DBG_RSTN_C0,
+ SW_RSTN_C0 | SW_DBG_RSTN_C0);
+}
+
diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.c b/sound/soc/sof/mediatek/mt8186/mt8186.c
index 60021195e0b5..892cd7d79994 100644
--- a/sound/soc/sof/mediatek/mt8186/mt8186.c
+++ b/sound/soc/sof/mediatek/mt8186/mt8186.c
@@ -204,6 +204,17 @@ static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
return 0;
}
+static int mt8186_run(struct snd_sof_dev *sdev)
+{
+ u32 adsp_bootup_addr;
+
+ adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
+ dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
+ sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
+
+ return 0;
+}
+
static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
{
struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
@@ -272,6 +283,7 @@ static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
{
+ sof_hifixdsp_shutdown(sdev);
adsp_sram_power_off(sdev);
return 0;
@@ -289,6 +301,9 @@ static struct snd_sof_dsp_ops sof_mt8186_ops = {
.probe = mt8186_dsp_probe,
.remove = mt8186_dsp_remove,
+ /* DSP core boot */
+ .run = mt8186_run,
+
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
@@ -302,6 +317,9 @@ static struct snd_sof_dsp_ops sof_mt8186_ops = {
/* misc */
.get_bar_index = mt8186_get_bar_index,
+ /* firmware loading */
+ .load_firmware = snd_sof_load_firmware_memcpy,
+
/* Firmware ops */
.dsp_arch_ops = &sof_xtensa_arch_ops,
diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.h b/sound/soc/sof/mediatek/mt8186/mt8186.h
index 40ea7cb9295b..df52ae9659e4 100644
--- a/sound/soc/sof/mediatek/mt8186/mt8186.h
+++ b/sound/soc/sof/mediatek/mt8186/mt8186.h
@@ -10,6 +10,7 @@
#define __MT8186_H
struct mtk_adsp_chip_info;
+struct snd_sof_dev;
#define DSP_REG_BAR 4
#define DSP_SECREG_BAR 5
@@ -74,4 +75,6 @@ struct mtk_adsp_chip_info;
#define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/
#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL)
+void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);
+void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);
#endif
--
2.18.0
Powered by blists - more mailing lists